From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8A13344D81 for ; Tue, 5 May 2026 10:18:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777976299; cv=none; b=iX2pTUy/VeDeYnGuThNo+2mthmePiGhcYiVNDe0eeQmSbt1+II+P68TaIzA7hdHmV/GioVZXkUrZRKPGncdHqysuSbcIf502yzBaqcCy4XUp3wOf+8rmBYQiKyQLr5kYWh8/CgBWMXFMD9lZTyN9eSLvs3Bto2WcDDS4J/PxoKM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777976299; c=relaxed/simple; bh=G7y66/eaN5CChlngDjIZOvc6r6dM5pR1CQdWqeGN11Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oKcrEEnUXm471DybWl8h5VmkpysW9xevuOUwY9BGIEABxpQRkyKiOzIY+LCKqY1f+8c+7U2ih5ecoCngkpV32U5HbHTvveWwfPtOTwCN8Un6IuSoJbr0qEA/3uHwViAhvo7I2iHd/UIMR9BNVMlOYpWWY8TH/IspURip6b3t6gU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J8+S68jL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J8+S68jL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5D2B2C2BCB4; Tue, 5 May 2026 10:18:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777976299; bh=G7y66/eaN5CChlngDjIZOvc6r6dM5pR1CQdWqeGN11Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J8+S68jLJOJSPJY1ybZXwtxguJ7ftjz3t1F/i9jjMsgg2OwwKWikZDfmpqUw0b5i1 VPkyatCF2rW9DYlFkGwVj5ajvVBPMLqhjqARgwlY6motUSvZk88HZJvOutJ+BD0Lg7 SE4R5fKrA4HizPCgdt7K99SXn3BUF3uf61DsHiTetBducYZfhiGGOKIX5oWJv4Wpqe PhQEocNmJkmHZMffYZwGUYA872rwOxOfM1Cex47vYm6VGg3c4tBdq37wzRBH9AerxB NMPD0QSwFaoZte9zzGWtTfb6j9+u5vwek6lL4XIrsQ00RSRhq4jXbFrUPYuP2dloxX kvIfLNNCQOaAg== From: Sasha Levin To: stable@vger.kernel.org Cc: Shawn Lin , Adrian Hunter , Ulf Hansson , Sasha Levin Subject: [PATCH 5.15.y] mmc: sdhci-of-dwcmshc: Disable clock before DLL configuration Date: Tue, 5 May 2026 06:18:15 -0400 Message-ID: <20260505101815.586456-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026050301-robe-placate-cf0b@gregkh> References: <2026050301-robe-placate-cf0b@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Shawn Lin [ Upstream commit 6546a49bbe656981d99a389195560999058c89c4 ] According to the ASIC design recommendations, the clock must be disabled before operating the DLL to prevent glitches that could affect the internal digital logic. In extreme cases, failing to do so may cause the controller to malfunction completely. Adds a step to disable the clock before DLL configuration and re-enables it at the end. Fixes: 08f3dff799d4 ("mmc: sdhci-of-dwcmshc: add rockchip platform support") Cc: stable@vger.kernel.org Signed-off-by: Shawn Lin Acked-by: Adrian Hunter Signed-off-by: Ulf Hansson [ dropped HS200/HS400 block and BIT(4) line, converted the single `return` in `if (clock <= 400000)` to `goto enable_clk` ] Signed-off-by: Sasha Levin --- drivers/mmc/host/sdhci-of-dwcmshc.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index eb7213a8b5ea8..088c6ffa6fb24 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -213,10 +213,13 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock extra &= ~BIT(0); sdhci_writel(host, extra, reg); + /* Disable clock while config DLL */ + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + if (clock <= 400000) { /* Disable DLL to reset sample clock */ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); - return; + goto enable_clk; } /* Reset DLL */ @@ -234,7 +237,7 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock 500 * USEC_PER_MSEC); if (err) { dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n"); - return; + goto enable_clk; } extra = 0x1 << 16 | /* tune clock stop en */ @@ -255,6 +258,16 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock DLL_STRBIN_TAPNUM_DEFAULT | DLL_STRBIN_TAPNUM_FROM_SW; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); + +enable_clk: + /* + * The sdclk frequency select bits in SDHCI_CLOCK_CONTROL are not functional + * on Rockchip's SDHCI implementation. Instead, the clock frequency is fully + * controlled via external clk provider by calling clk_set_rate(). Consequently, + * passing 0 to sdhci_enable_clk() only re-enables the already-configured clock, + * which matches the hardware's actual behavior. + */ + sdhci_enable_clk(host, 0); } static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) -- 2.53.0