From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EC4433C182 for ; Tue, 5 May 2026 10:33:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777977217; cv=none; b=ICLP+KxlKMpSOdGuUWBKW09dgjStCIGxgapxaUvvweEFc8+tV9xpoEf+OoP0b1tm0rrrfsoboHFyExnJ0dJv7l0iHZlxCaGUpQbw1UCvxO6Zddr5QW/Ov5OHPDwDexD8gsVkdrEupLE8xLSzKH+fRKj7RgtcYIy0bu9C/2K9940= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777977217; c=relaxed/simple; bh=K8vDP7IFJfwPRk//oVOU5e5kBzyy3SELlQVb4iPkY3o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tU4ltvJqafxFaufVnpim6RebkNRhiE6cqJK8A+TVe+LKYOE2gAQeCSO8UWvNTL+wYArJiLxFlkCjUlEAM1TsnxvrqKIzhOoJsQgc10e/v6wU7pC7d2nTsP8p6bB5YFQGgDIb/fg8NKPw2ZZYNlWb1/Kmx7in3j1ZeCfbmAo6M4k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ofqMx4/G; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ofqMx4/G" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 51680C2BCB9; Tue, 5 May 2026 10:33:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777977216; bh=K8vDP7IFJfwPRk//oVOU5e5kBzyy3SELlQVb4iPkY3o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ofqMx4/GDQkQQ039Xh/t3tRzImpWT2Hn2DqRNmHxetE73rR+L6XfvAVFPdRxwcEyT YThb9m5ehREjow6eroJAHQGvUCzcTgwHi591R+CY5wuIybHv0FqU47Qh5zgZt5bjZ6 0O6x6vaUJ78mmQDTuPVdkCFk04qRPZGyKjGhsEjmRROJR09FvQwTXsqSRTvXzAriJw 3K4XuHxocpjP44ydsu0UvR2kpXGN6wLppkw1BXWLVDpdRyJPg70B26LBuJVwPcME9f O2vvq9Fl7r/XG2QzR0nQiJzxaaQU9JBP3lRgD/z3jY+QY/1HnUeSVX8f6QwvMlO1gs igCwgFPy/wnxQ== From: Sasha Levin To: stable@vger.kernel.org Cc: Suman Kumar Chakraborty , Giovanni Cabiddu , Herbert Xu , Sasha Levin Subject: [PATCH 6.18.y 1/2] crypto: qat - fix indentation of macros in qat_hal.c Date: Tue, 5 May 2026 06:33:29 -0400 Message-ID: <20260505103330.596817-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026050339-trapped-replace-1e60@gregkh> References: <2026050339-trapped-replace-1e60@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Suman Kumar Chakraborty [ Upstream commit 4963b39e3a3feed07fbf4d5cc2b5df8498888285 ] The macros in qat_hal.c were using a mixture of tabs and spaces. Update all macro indentation to use tabs consistently, matching the predominant style. This does not introduce any functional change. Signed-off-by: Suman Kumar Chakraborty Reviewed-by: Giovanni Cabiddu Signed-off-by: Herbert Xu Stable-dep-of: e7dcb722bb75 ("crypto: qat - fix firmware loading failure for GEN6 devices") Signed-off-by: Sasha Levin --- drivers/crypto/intel/qat/qat_common/qat_hal.c | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/crypto/intel/qat/qat_common/qat_hal.c b/drivers/crypto/intel/qat/qat_common/qat_hal.c index da4eca6e1633e..614400e7bb0ac 100644 --- a/drivers/crypto/intel/qat/qat_common/qat_hal.c +++ b/drivers/crypto/intel/qat/qat_common/qat_hal.c @@ -9,17 +9,17 @@ #include "icp_qat_hal.h" #include "icp_qat_uclo.h" -#define BAD_REGADDR 0xffff -#define MAX_RETRY_TIMES 10000 -#define INIT_CTX_ARB_VALUE 0x0 -#define INIT_CTX_ENABLE_VALUE 0x0 -#define INIT_PC_VALUE 0x0 -#define INIT_WAKEUP_EVENTS_VALUE 0x1 -#define INIT_SIG_EVENTS_VALUE 0x1 -#define INIT_CCENABLE_VALUE 0x2000 -#define RST_CSR_QAT_LSB 20 -#define RST_CSR_AE_LSB 0 -#define MC_TIMESTAMP_ENABLE (0x1 << 7) +#define BAD_REGADDR 0xffff +#define MAX_RETRY_TIMES 10000 +#define INIT_CTX_ARB_VALUE 0x0 +#define INIT_CTX_ENABLE_VALUE 0x0 +#define INIT_PC_VALUE 0x0 +#define INIT_WAKEUP_EVENTS_VALUE 0x1 +#define INIT_SIG_EVENTS_VALUE 0x1 +#define INIT_CCENABLE_VALUE 0x2000 +#define RST_CSR_QAT_LSB 20 +#define RST_CSR_AE_LSB 0 +#define MC_TIMESTAMP_ENABLE (0x1 << 7) #define IGNORE_W1C_MASK ((~(1 << CE_BREAKPOINT_BITPOS)) & \ (~(1 << CE_CNTL_STORE_PARITY_ERROR_BITPOS)) & \ -- 2.53.0