From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F60026A1CF for ; Thu, 14 May 2026 18:33:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778783619; cv=none; b=XfOVeyliOQFPtGUqKJEAnyCAl1lz1atCbg/SLg3jFhGih4c/PZqVpQXkvmPaVSu3y7ExLAs7DhedAH4aMLYkQiBqkcLvWKb0OMdv6R5ib49o4f9odVbpbkzbqHu6IeIlsvu8H+tjPWFMQVMEhiMsjyxsyM5NbjobggnKN2D68bw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778783619; c=relaxed/simple; bh=/GMNYDHXvhOnRud+C7bnHWFdX6n7IuqdEQE9Xx84cLk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OUKqr6EFBSUBws0icdwTRaJgtsjRrESzPjF1KF9VrnwrrfJO0dATdZ+OGXzELp1vlutqgVvR99uAjIMEl4uGqicZPKfGzDyv7h9U7dN5WMUMoluBFSS/3+BxSaOffqVn5CO6e7GRl+IEUXsyHLjpsTTRuJFwk/viPOkBqqyYzxs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HszNbVaD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HszNbVaD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A1267C2BCB3; Thu, 14 May 2026 18:33:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778783619; bh=/GMNYDHXvhOnRud+C7bnHWFdX6n7IuqdEQE9Xx84cLk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HszNbVaD4aYoX1v4ABU2oEGVw0qF35l8qcoLUBISH5NRGF1IvJ4WOa/+l7hVBxDWF 6XnTglz2bC9YP5Lg4AGwKdMsBBdIrLPjUVyxxPkDsmw2ZMZPoVGsQZGdxR17+VMt3E ukoXX36V/Nt0srF7udibqpMQMRe0/x+v/NVPBR5OlUbEQHNazRvm0qG8f6A5uDQoNF Mbxq9keRRi480HCzKIQE82pyQruVvCqnZ5hC0mrKsjpSQwwqeiN1/yoXtLtSycp7QQ njsZkqzqoFCWDxm15NMzP3jgZGDtJvxMZEwMs8ek0oLksvzNZCPolEuAgZBlsMdXls 5IuC5BDw/VZvA== From: Sasha Levin To: stable@vger.kernel.org Cc: Li Zetao , Jonathan Cameron , Mark Brown , Sasha Levin Subject: [PATCH 6.6.y 1/2] spi: microchip-core-qspi: Use helper function devm_clk_get_enabled() Date: Thu, 14 May 2026 14:33:35 -0400 Message-ID: <20260514183336.771790-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026051251-shrimp-duller-1ca2@gregkh> References: <2026051251-shrimp-duller-1ca2@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Li Zetao [ Upstream commit e922f3fff21445117e9196bd8e940ad8e15ca8c7 ] Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly. Reviewed-by: Jonathan Cameron Signed-off-by: Li Zetao Link: https://lore.kernel.org/r/20230823133938.1359106-18-lizetao1@huawei.com Signed-off-by: Mark Brown Stable-dep-of: e6464140d439 ("spi: microchip-core-qspi: fix controller deregistration") Signed-off-by: Sasha Levin --- drivers/spi/spi-microchip-core-qspi.c | 29 +++++++-------------------- 1 file changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microchip-core-qspi.c index 32a0fa4ba50f7..0e44683d5ab5e 100644 --- a/drivers/spi/spi-microchip-core-qspi.c +++ b/drivers/spi/spi-microchip-core-qspi.c @@ -519,30 +519,23 @@ static int mchp_coreqspi_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(qspi->regs), "failed to map registers\n"); - qspi->clk = devm_clk_get(&pdev->dev, NULL); + qspi->clk = devm_clk_get_enabled(&pdev->dev, NULL); if (IS_ERR(qspi->clk)) return dev_err_probe(&pdev->dev, PTR_ERR(qspi->clk), "could not get clock\n"); - ret = clk_prepare_enable(qspi->clk); - if (ret) - return dev_err_probe(&pdev->dev, ret, - "failed to enable clock\n"); - init_completion(&qspi->data_completion); mutex_init(&qspi->op_lock); qspi->irq = platform_get_irq(pdev, 0); - if (qspi->irq < 0) { - ret = qspi->irq; - goto out; - } + if (qspi->irq < 0) + return qspi->irq; ret = devm_request_irq(&pdev->dev, qspi->irq, mchp_coreqspi_isr, IRQF_SHARED, pdev->name, qspi); if (ret) { dev_err(&pdev->dev, "request_irq failed %d\n", ret); - goto out; + return ret; } ctlr->bits_per_word_mask = SPI_BPW_MASK(8); @@ -553,18 +546,11 @@ static int mchp_coreqspi_probe(struct platform_device *pdev) ctlr->dev.of_node = np; ret = devm_spi_register_controller(&pdev->dev, ctlr); - if (ret) { - dev_err_probe(&pdev->dev, ret, - "spi_register_controller failed\n"); - goto out; - } + if (ret) + return dev_err_probe(&pdev->dev, ret, + "spi_register_controller failed\n"); return 0; - -out: - clk_disable_unprepare(qspi->clk); - - return ret; } static void mchp_coreqspi_remove(struct platform_device *pdev) @@ -575,7 +561,6 @@ static void mchp_coreqspi_remove(struct platform_device *pdev) mchp_coreqspi_disable_ints(qspi); control &= ~CONTROL_ENABLE; writel_relaxed(control, qspi->regs + REG_CONTROL); - clk_disable_unprepare(qspi->clk); } static const struct of_device_id mchp_coreqspi_of_match[] = { -- 2.53.0