From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05CC544CAEC for ; Fri, 15 May 2026 11:46:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778845572; cv=none; b=JRqg6zh+FvrscFC3tRipKAsrLCgtFs0FngLIS3NttZo2rafuSuzzGaR3vFDFQ5twgVhjSOdbvPA8YIbHQ1H/uPZ3o4vDRv0qRFPmUY7ZiAjeCWNxMtvmrmYp1XvWSDlfxbcetcE8CMi9oVVKADNkXp0FOykEF6Sf0VI3XxSqDu8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778845572; c=relaxed/simple; bh=4VK4oXnlgxjBzxU9bb2HufvF2ufwQYe4aqVBcqfMIyI=; h=Subject:To:From:Date:Message-ID:MIME-Version:Content-Type; b=CIxPGsfwkulQumHPZ1wiosfFW7msPUqMtLsfwZwsWJ8/otO8XwnbkDZwh5px3D7WwgEkdDH45PyXUT1f843NvwG8dTEimkHIrHn/H9w1wBYwCq7E8+Fp4sEdXPr37UViHjBcuWAVbxwVI3O7zLz13h7wbEHq0utITKuElFtaTMU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=zZN7Gqy+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="zZN7Gqy+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31D8BC2BCB0; Fri, 15 May 2026 11:46:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1778845571; bh=4VK4oXnlgxjBzxU9bb2HufvF2ufwQYe4aqVBcqfMIyI=; h=Subject:To:From:Date:From; b=zZN7Gqy+IqmAYqzVuSJo9/3Ko9MttLQlvjQHzP+s4+2K7eAKrESR89D7A+5BrR3Jr FFeOITLScMcSJzM4+yhfkfxDrUpIpfrxwTXzGtpoflRsC8k8zhTyTgEG8Gd4zXOIHB H5gRypEGGWJqBge53DTqh9zWzKIzyxO5C1qxEb9M= Subject: patch "iio: adc: nxp-sar-adc: fix division by zero in write_raw" added to char-misc-linus To: antoniu.miclaus@analog.com,Stable@vger.kernel.org,jic23@kernel.org From: Date: Fri, 15 May 2026 13:45:56 +0200 Message-ID: <2026051556-skiing-poison-e81b@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit This is a note to let you know that I've just added the patch titled iio: adc: nxp-sar-adc: fix division by zero in write_raw to my char-misc git tree which can be found at git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git in the char-misc-linus branch. The patch will show up in the next release of the linux-next tree (usually sometime within the next 24 hours during the week.) The patch will hopefully also be merged in Linus's tree for the next -rc kernel release. If you have any questions about this process, please let me know. >From a9aba21a539c668a66b58eeb08ad3909e5a54c2a Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Wed, 1 Apr 2026 18:29:24 +0300 Subject: iio: adc: nxp-sar-adc: fix division by zero in write_raw Add a validation check for the sampling frequency value before using it as a divisor. A user writing zero or a negative value to the sampling_frequency sysfs attribute triggers a division by zero in the kernel. Also prevent unsigned integer underflow when the computed cycle count is smaller than NXP_SAR_ADC_CONV_TIME, which would wrap the u32 inpsamp to a huge value. Fixes: 4434072a893e ("iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms") Signed-off-by: Antoniu Miclaus Cc: Signed-off-by: Jonathan Cameron --- drivers/iio/adc/nxp-sar-adc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/nxp-sar-adc.c b/drivers/iio/adc/nxp-sar-adc.c index 705dd7da1bd2..1711cae7d872 100644 --- a/drivers/iio/adc/nxp-sar-adc.c +++ b/drivers/iio/adc/nxp-sar-adc.c @@ -569,6 +569,9 @@ static int nxp_sar_adc_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec switch (mask) { case IIO_CHAN_INFO_SAMP_FREQ: + if (val <= 0) + return -EINVAL; + /* * Configures the sample period duration in terms of the SAR * controller clock. The minimum acceptable value is 8. @@ -577,7 +580,11 @@ static int nxp_sar_adc_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec * sampling timing which gives us the number of cycles expected. * The value is 8-bit wide, consequently the max value is 0xFF. */ - inpsamp = clk_get_rate(info->clk) / val - NXP_SAR_ADC_CONV_TIME; + inpsamp = clk_get_rate(info->clk) / val; + if (inpsamp < NXP_SAR_ADC_CONV_TIME) + return -EINVAL; + + inpsamp -= NXP_SAR_ADC_CONV_TIME; nxp_sar_adc_conversion_timing_set(info, inpsamp); return 0; -- 2.54.0