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(host-127-24.cafrjco.fresno.ca.us.clients.pavlovmedia.net. [68.180.127.24]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302973bc8ddsm12335857eec.21.2026.05.17.18.49.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 May 2026 18:49:39 -0700 (PDT) From: Ethan Nelson-Moore To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Ethan Nelson-Moore , stable@vger.kernel.org, Russell King , "Russell King (Oracle)" , Arnd Bergmann , Linus Walleij , Kees Cook , Nathan Chancellor , Thomas Weissschuh , Peter Zijlstra , Shubham Bansal , "David S. Miller" Subject: [PATCH] ARM: disable broken eBPF JIT on the Risc PC Date: Sun, 17 May 2026 18:49:17 -0700 Message-ID: <20260518014920.135011-1-enelsonmoore@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The eBPF JIT unconditionally generates ldrh/strh instructions, which do not function correctly on the Risc PC because its bus is unable to signal half-word accesses. Work around this issue by disabling the eBPF JIT when building for ARMv3 (the Risc PC is the only currently supported ARMv3 machine). Fixes: 39c13c204bb1 ("arm: eBPF JIT compiler") Cc: stable@vger.kernel.org Signed-off-by: Ethan Nelson-Moore --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1155c78bb6aa..8185d013e5d1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -98,7 +98,7 @@ config ARM select HAVE_ARCH_TRACEHOOK select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE select HAVE_ARM_SMCCC if CPU_V7 - select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 + select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 && !CPU_32v3 select HAVE_CONTEXT_TRACKING_USER select HAVE_C_RECORDMCOUNT select HAVE_BUILDTIME_MCOUNT_SORT -- 2.43.0