From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA9733B6BFE for ; Fri, 29 May 2026 08:03:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780041825; cv=none; b=aGfe0wJRAUE/sQgZ4Qv+m2HzWQvFss5SnEOK97tXyaSfzEg5/Oci2AOZNPheicrPVGnpx6Z9ERyJK3PnCxas+4ZDHalMy/Fv5hF6UxzchRzJjimzkM4CKrQbKfCOcjyEDh9JtJbxPgz+EY5ILGvLvDTNpqzTJ3tpO8vlgADE2y8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780041825; c=relaxed/simple; bh=NEqbIOhrxcFFKAZpTx5n47Vd1HYn6Oo6l0+Xp+rYT6s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=re+r0YKrxHskd5hb59GUxHbFA2OOardObpAzf45wyZODP441DiLCyxxy2ut2rkQbvGgi7Q/C26AMr3d8ii9gdFVUMUSmt4vcYobDMKpHYAMhbeagKg7ecnFB4Bjo23STKJhvYdbKqwGvHL+N2yGgWbKNh11oo2rR6miGSERfXGA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BKb4v2Fx; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BKb4v2Fx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780041820; x=1811577820; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NEqbIOhrxcFFKAZpTx5n47Vd1HYn6Oo6l0+Xp+rYT6s=; b=BKb4v2FxTrdWj16rWzYWDSHh38zA79divQDz4+m23HH255qgUU7lWt4b jjonWM+Pv6fF5vyK5gBr8gnXdcl63eGw39g56GuXSB3UJP8TLD4fprmmy ueEh8Dq8B7e17cw4HTg4YYm8SZmgMWZ0nqHZxyIOyMUXVlxAezCe960hS UV49QVrQ0siNTtYVLL6Pa0bY3ujDeNrvkCf8D5/HZ/dL++U/eAYFxuiwa vUMCqtjulQFHJR5eHXnUszJttEzBK/HHWBbotO+d1fBi73g7ZP4cygG46 Qx/EosTWw6+XtMAmyQwOHFvei3fGTrrb5a46YcRBFOI1vcXu0ee9P90QP A==; X-CSE-ConnectionGUID: i3jQZhmfSlqBRn/R/vUJvw== X-CSE-MsgGUID: gsjk96mkTN2seX9SpQH5dQ== X-IronPort-AV: E=McAfee;i="6800,10657,11800"; a="81073755" X-IronPort-AV: E=Sophos;i="6.24,175,1774335600"; d="scan'208";a="81073755" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2026 01:03:40 -0700 X-CSE-ConnectionGUID: Wff0vm3YRamfkvj4a2W5FQ== X-CSE-MsgGUID: b9OxQ2T7Q+yPX+iP+Zst9w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,175,1774335600"; d="scan'208";a="247726766" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO jhogande-mobl3.intel.com) ([10.245.246.54]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2026 01:03:38 -0700 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: stable@vger.kernel.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= , Suraj Kandpal , Tvrtko Ursulin Subject: [PATCH 5.15.y 2/4] drm/i915/psr: Read Intel DPCD workaround register Date: Fri, 29 May 2026 11:03:15 +0300 Message-ID: <20260529080317.343937-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529080317.343937-1-jouni.hogander@intel.com> References: <2026052830-confirm-prepaid-2f4e@gregkh> <20260529080317.343937-1-jouni.hogander@intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit commit f30bece421a4ae34359254e1dc2a187a42b6af9b upstream. Read Intel DPCD workaround register and store it into intel_connector->dp.psr_caps. psr_caps was chosen as currently it contains only PSR workaround for PSR2 SDP on prior scanline implementation. Signed-off-by: Jouni Högander Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/20260515095756.2799483-3-jouni.hogander@intel.com (cherry picked from commit c48ff24d0f4ab7ad696b2d35ad64ce7e049c668c) Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 90e055f05699..ef4c280d2cb6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1554,6 +1554,7 @@ struct intel_dp { u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; u8 fec_capable; u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; + u8 intel_wa_dpcd; /* source rates */ int num_source_rates; const int *source_rates; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 93d2fd4cd16b..aa00e062a2a6 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -30,6 +30,7 @@ #include "intel_atomic.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_dpcd.h" #include "intel_dp_aux.h" #include "intel_hdmi.h" #include "intel_psr.h" @@ -363,6 +364,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) intel_dp_get_su_granularity(intel_dp); } } + + if (intel_dp->psr.sink_psr2_support) + drm_dp_dpcd_read(&intel_dp->aux, + INTEL_DPCD_INTEL_WA_REGISTER_CAPS, + &intel_dp->intel_wa_dpcd, + sizeof(intel_dp->intel_wa_dpcd)); } static void hsw_psr_setup_aux(struct intel_dp *intel_dp) -- 2.43.0