From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77CB73BA22E for ; Fri, 29 May 2026 09:06:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780045616; cv=none; b=ZSHPdcllgScSAQn1AwY0uhvXwittHZoNN/cihx6n1k0B9fve2hzsLCluP0mBdf9HgNms+WTeK9gAr1CwRYuTiAlPwGX+KMQjEyJdRYNMe0xnberA8HnTN7WieFPXOh3XPoffyhrCxMwHeIbGjraJG0pJvy7xpviSVgDBs/dgYWw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780045616; c=relaxed/simple; bh=7RXmNSiUwSPacY4yXPou7y0pYLCnJNUvs9p3IP2X9iA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nJT8/75INAZ49GUAwVIjIXAqC3IVaQRANrO/EJ1kTdQehMxQfl9NFQM5cGPRhSmSVLV1Yf+ieOF3JUdOW2uybSv4P7xD+BsZq3c6OoO3wTTgVPXZt4JDsLmtzaVLDDvJQ5iWYzhv+xe7M3a+5i87uAAlGzOtTo8F2WU/ctb0r+Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=UFFn+5IB; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UFFn+5IB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780045615; x=1811581615; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7RXmNSiUwSPacY4yXPou7y0pYLCnJNUvs9p3IP2X9iA=; b=UFFn+5IB3qTnS0AkU9NoopG9XdTMVDRsGNNv6K+JCoD1kEKJdiZziRXM oiY7S2DWCV9LkMWiF3HzNRBxcneY7wzMPvW2YyQylVq6mI7uuGzRo47xp LYjTK87NCgwzVy9/ct3iSFMJoQRD3RbCC9f2uSmdl5WpT9z11celEYZVU LaTArpr4HefLztFR5VwxWjwdswVY+mNuP/KgswqZRLVn/aDVxVoBbKZCF KPRwHq4NiYfQ2f8zDeDP6HzjhKBJ5gMQf9vY3vFmnzMvUefVA/jRZsKdd c084HTmqTuIRhr7bk7Mhm3O5JDIGMLilZa/1mrb8swsw0s95dV8q55LB1 g==; X-CSE-ConnectionGUID: lcLWAg1kQOiAQ4skuvtoCA== X-CSE-MsgGUID: 2FUMfjxWRKOlaKamwPAwYA== X-IronPort-AV: E=McAfee;i="6800,10657,11800"; a="84520490" X-IronPort-AV: E=Sophos;i="6.24,175,1774335600"; d="scan'208";a="84520490" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2026 02:06:55 -0700 X-CSE-ConnectionGUID: Op5BZ4YjTxG45Yj2zWIAIQ== X-CSE-MsgGUID: aer+dc87TMm33BgFbiTLPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,175,1774335600"; d="scan'208";a="241987036" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO jhogande-mobl3.intel.com) ([10.245.246.54]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2026 02:06:53 -0700 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: stable@vger.kernel.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= , Suraj Kandpal , Tvrtko Ursulin Subject: [PATCH 6.6.y 2/4] drm/i915/psr: Read Intel DPCD workaround register Date: Fri, 29 May 2026 12:06:34 +0300 Message-ID: <20260529090636.530204-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529090636.530204-1-jouni.hogander@intel.com> References: <2026052827-tweezers-colonize-3631@gregkh> <20260529090636.530204-1-jouni.hogander@intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit commit f30bece421a4ae34359254e1dc2a187a42b6af9b upstream. Read Intel DPCD workaround register and store it into intel_connector->dp.psr_caps. psr_caps was chosen as currently it contains only PSR workaround for PSR2 SDP on prior scanline implementation. Signed-off-by: Jouni Högander Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/20260515095756.2799483-3-jouni.hogander@intel.com (cherry picked from commit c48ff24d0f4ab7ad696b2d35ad64ce7e049c668c) Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1c23b186aff2..3a228cfb1550 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1719,6 +1719,7 @@ struct intel_dp { u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; u8 fec_capable; u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; + u8 intel_wa_dpcd; /* source rates */ int num_source_rates; const int *source_rates; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b0818dc8480e..49842f7877f4 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -31,6 +31,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_dp.h" +#include "intel_dpcd.h" #include "intel_dp_aux.h" #include "intel_hdmi.h" #include "intel_psr.h" @@ -528,6 +529,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) intel_dp_get_su_granularity(intel_dp); } } + + if (intel_dp->psr.sink_psr2_support) + drm_dp_dpcd_read(&intel_dp->aux, + INTEL_DPCD_INTEL_WA_REGISTER_CAPS, + &intel_dp->intel_wa_dpcd, + sizeof(intel_dp->intel_wa_dpcd)); } static void hsw_psr_setup_aux(struct intel_dp *intel_dp) -- 2.43.0