From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A1BC217F27 for ; Fri, 29 May 2026 10:06:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780049190; cv=none; b=NaJx6J+23ySOx+Ztxdj2dRV9q7Grfb6EHwpVEa+ZNW56SxfEBC0Lvo+otKTJgM6K+MW97rbx5gIWpHUH/C65WwegiYiBlUCTuxN7Jy0z5hK3GQxhwIa37ixnKVd8aou7UdHrVLPHUOJ/bTgzGsBdl+/TRZftU4FOhqx5r4E1Rd0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780049190; c=relaxed/simple; bh=pgiDeSYsVAvt4wHksuKeTGr45HVvGZjfZ6TrolOuOZc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eVK9J7gpp6xeS1Whm1VwkXDMcWGIutT4O7pH3qN+dWVzpsmmiR9hYMGGx8Uf4/4zYFWkR+PhhaE1DWgUZS85gGiJPhliTgCTDXKHqlw6G0hK041Fwynef4NactvpQAtNv80lm3xuVP2AWa/WhOMyBfz9JVDu+rLLzuxRyVQYoVQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=B/X7Pagk; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="B/X7Pagk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780049189; x=1811585189; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pgiDeSYsVAvt4wHksuKeTGr45HVvGZjfZ6TrolOuOZc=; b=B/X7PagkdsbCNmewNbizPLnmLvG0l10OFrOZcyz+8W2rxZjSn0oALQJx wNZTuQbVlB+WB4hE/HDfEgo7SL17oj3oelXu1cVO5KD3mj8w65QKRyGOy veYOC6m+ZLvPg4OgjJvw1BfQHaHZFw7bVRb+cvLZoiwXLxYmfdRuogwRw rzg7eVfE044ZG/Kendjf1r3VR0UIz57EOa8IWPp40LUT3elOn44H3TDe9 Afy8EVFF9oZ69dJxKcgS30JDzwcw0G8jmYloQBVz5lemQkVUMXoFkjtDA FQsVZ6RvYilkCgtHNrwlbjn7yVYOXreAmBtqDHIt2CMgYM48PdqPHqfMF A==; X-CSE-ConnectionGUID: FAR6t6p3QNWVMBpbTyf+PQ== X-CSE-MsgGUID: DmS9Nqv8TlmR7JBImlqlYg== X-IronPort-AV: E=McAfee;i="6800,10657,11800"; a="84759125" X-IronPort-AV: E=Sophos;i="6.24,175,1774335600"; d="scan'208";a="84759125" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2026 03:06:28 -0700 X-CSE-ConnectionGUID: pMRcRyoqT1WDAWEKTOgTHQ== X-CSE-MsgGUID: +3ZaA1NcR966iq2enReh1A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,175,1774335600"; d="scan'208";a="244631543" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO jhogande-mobl3.intel.com) ([10.245.246.54]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2026 03:06:27 -0700 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: stable@vger.kernel.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= , Suraj Kandpal , Tvrtko Ursulin Subject: [PATCH 6.18.y 2/3] drm/i915/psr: Read Intel DPCD workaround register Date: Fri, 29 May 2026 13:06:12 +0300 Message-ID: <20260529100613.686720-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529100613.686720-1-jouni.hogander@intel.com> References: <2026052816-gigolo-dense-47c7@gregkh> <20260529100613.686720-1-jouni.hogander@intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit commit f30bece421a4ae34359254e1dc2a187a42b6af9b upstream. Read Intel DPCD workaround register and store it into intel_connector->dp.psr_caps. psr_caps was chosen as currently it contains only PSR workaround for PSR2 SDP on prior scanline implementation. Signed-off-by: Jouni Högander Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/20260515095756.2799483-3-jouni.hogander@intel.com (cherry picked from commit c48ff24d0f4ab7ad696b2d35ad64ce7e049c668c) Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 39dd7389f1a7..197bdb6592a7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1710,6 +1710,7 @@ struct intel_dp { u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; + u8 intel_wa_dpcd; /* source rates */ int num_source_rates; const int *source_rates; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1da20065ea77..802a671b2afa 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -41,6 +41,7 @@ #include "intel_display_types.h" #include "intel_dmc.h" #include "intel_dp.h" +#include "intel_dpcd.h" #include "intel_dp_aux.h" #include "intel_dsb.h" #include "intel_frontbuffer.h" @@ -679,6 +680,12 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp) drm_dbg_kms(display->drm, "PSR2 %ssupported\n", intel_dp->psr.sink_psr2_support ? "" : "not "); } + + if (intel_dp->psr.sink_psr2_support) + drm_dp_dpcd_read(&intel_dp->aux, + INTEL_DPCD_INTEL_WA_REGISTER_CAPS, + &intel_dp->intel_wa_dpcd, + sizeof(intel_dp->intel_wa_dpcd)); } void intel_psr_init_dpcd(struct intel_dp *intel_dp) -- 2.43.0