From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1DA934040B for ; Fri, 29 May 2026 10:06:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780049192; cv=none; b=YbhnhcJGx2w8Le20LicNXJssvOes1T2Y5XgJweWQTpQ03CxaRKfWAyuq70bSPSDCrcGnVqDh9sezAqxvYBkKnJ+sY4iZBBlkM0eHXcokp5i0fG9zIhuQLi3+H7u2YbEFL+32IEWi8JtHSbqTCw6vHLK+NmcEl5TmCGc35wCMnPM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780049192; c=relaxed/simple; bh=bs1QpK5yV0eU1cyQijfSYNhROFQ6HjjmB5q9C/2D6QI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nvJB5AzNW9XLYmHlh7Kw4u29K8hSpNgvZhDTakh6jiZd43JADEyTYNk0lh6qYjDMmUwfh4Y9HtDAYuLWsMlGbgur21Rcu8GyDqXKwQjwIpw2bilWRmic2Qd0eYcLTwPSwTzEbe5ZzTYoV5sE3LaMfNOJgp05uxK3oGlU4vB0rzg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EUDdLFl1; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EUDdLFl1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780049191; x=1811585191; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bs1QpK5yV0eU1cyQijfSYNhROFQ6HjjmB5q9C/2D6QI=; b=EUDdLFl1BPZA66myWhXdHlUwM8hTIrJyv/57tq/dpq+zqhsazGFlnDBc 2dgb4Rot5+5zZOcEtkB8k7G+9nSk8IDZbBK7MBbFJZ6rTRvNW961Ts+R8 t1AStlWO9hC7lvGXuI/OTCcW15BBqDvbpMdvTcB/oT+tgq6MmnGVxNzLA fbZUGT7zflaFKAUP38v1iMcFrA+qhUs2RJvSBJ6QGXQDJYLitvKYLhcfl SFYRSFGF7FBwD69LnQ+t1H3+2667sltQ2+wnV7O/AnxRYhxLG1lqmj08g cQ8mBAmWKhiAPUtew+aXHGRpirmgmrSranZUXlro+OavqSmfa5xeVAC+x g==; X-CSE-ConnectionGUID: OPe+0I7wSoubw+61LVIo1g== X-CSE-MsgGUID: AjUHSE8rSbWeoWMHggTXog== X-IronPort-AV: E=McAfee;i="6800,10657,11800"; a="84759128" X-IronPort-AV: E=Sophos;i="6.24,175,1774335600"; d="scan'208";a="84759128" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2026 03:06:30 -0700 X-CSE-ConnectionGUID: UyarV7h4SWq/qdDabe2GFw== X-CSE-MsgGUID: IOAWRDM7RkWlxUZk89Rbvg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,175,1774335600"; d="scan'208";a="244631548" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO jhogande-mobl3.intel.com) ([10.245.246.54]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2026 03:06:29 -0700 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: stable@vger.kernel.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= , Suraj Kandpal , Tvrtko Ursulin Subject: [PATCH 6.18.y 3/3] drm/i915/psr: Apply Intel DPCD workaround when SDP on prior line used Date: Fri, 29 May 2026 13:06:13 +0300 Message-ID: <20260529100613.686720-3-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529100613.686720-1-jouni.hogander@intel.com> References: <2026052816-gigolo-dense-47c7@gregkh> <20260529100613.686720-1-jouni.hogander@intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit commit 4703049f768fc1c1caac754134118bee1a3af189 upstream. There is Intel specific workaround DPCD address containing workaround for case where SDP is on prior line. Apply this workaround according to values in the offset. Fixes: 61e887329e33 ("drm/i915/xelpd: Handle PSR2 SDP indication in the prior scanline") Cc: # v5.15+ Signed-off-by: Jouni Högander Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/20260515095756.2799483-4-jouni.hogander@intel.com (cherry picked from commit c3fe899fbeac86ea4a5ca9dd845b2cbc0da46249) Signed-off-by: Tvrtko Ursulin Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 28 +++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 802a671b2afa..eed281b93cd8 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -29,6 +29,7 @@ #include #include "i915_reg.h" +#include "i915_utils.h" #include "intel_alpm.h" #include "intel_atomic.h" #include "intel_crtc.h" @@ -1315,6 +1316,30 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp, return true; } +static bool apply_scanline_indication_wa(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + u8 early_scanline_support = intel_dp->intel_wa_dpcd & + INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_EARLYSCANLINE_SDP_SUPPORT_MASK; + + if (intel_dp->edp_dpcd[0] >= DP_EDP_15) + return true; + + switch (early_scanline_support) { + case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_FALL_BACK_TO_PSR1: + crtc_state->req_psr2_sdp_prior_scanline = false; + return false; + case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITH_EARLY_SCANLINE: + return true; + case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITHOUT_EARLY_SCANLINE: + crtc_state->req_psr2_sdp_prior_scanline = false; + return true; + default: + MISSING_CASE(early_scanline_support); + return false; + } +} + static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -1336,7 +1361,8 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d return false; crtc_state->req_psr2_sdp_prior_scanline = true; - return true; + + return apply_scanline_indication_wa(intel_dp, crtc_state); } static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, -- 2.43.0