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[188.141.5.72]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4601f35133csm56677372f8f.25.2026.06.08.22.32.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2026 22:32:33 -0700 (PDT) From: David Carlier To: Daniel Scally , Jacopo Mondi Cc: Mauro Carvalho Chehab , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, David Carlier , stable@vger.kernel.org Subject: [PATCH] media: mali-c55: Fix AEXP IHIST disable bit shift Date: Tue, 9 Jun 2026 06:32:31 +0100 Message-ID: <20260609053231.24855-1-devnexen@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The post-Iridix auto-exposure histogram disable bit in MALI_C55_REG_METERING_CONFIG is bit 16, but MALI_C55_AEXP_IHIST_DISABLE was defined with a shift of 12, copied from the AEXP_HIST definition above it. As the value is masked with the BIT(16) disable mask when it is programmed, the result is always zero and the disable bit is never set. The IHIST can therefore never be disabled, neither at ISP init nor via a parameters block flagged V4L2_ISP_PARAMS_FL_BLOCK_DISABLE, and the hardware keeps producing histogram statistics that userspace believes are switched off. Use a shift of 16 so the disable request takes effect. Fixes: d5f281f3dd29 ("media: mali-c55: Add Mali-C55 ISP driver") Cc: stable@vger.kernel.org Assisted-by: Claude:claude-opus-4-8 Signed-off-by: David Carlier --- drivers/media/platform/arm/mali-c55/mali-c55-registers.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/arm/mali-c55/mali-c55-registers.h b/drivers/media/platform/arm/mali-c55/mali-c55-registers.h index f098effde..4cd13b702 100644 --- a/drivers/media/platform/arm/mali-c55/mali-c55-registers.h +++ b/drivers/media/platform/arm/mali-c55/mali-c55-registers.h @@ -173,7 +173,7 @@ enum mali_c55_interrupts { #define MALI_C55_AEXP_HIST_SWITCH_MASK GENMASK(14, 13) #define MALI_C55_AEXP_HIST_SWITCH(x) ((x) << 13) #define MALI_C55_AEXP_IHIST_DISABLE_MASK BIT(16) -#define MALI_C55_AEXP_IHIST_DISABLE (0x01 << 12) +#define MALI_C55_AEXP_IHIST_DISABLE (0x01 << 16) #define MALI_C55_AEXP_SRC_MASK BIT(24) #define MALI_C55_REG_TPG_CH0 0x18ed8 -- 2.53.0