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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2b0c35sm24759410f8f.22.2026.06.14.04.58.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Jun 2026 04:58:58 -0700 (PDT) Date: Sun, 14 Jun 2026 12:58:57 +0100 From: David Laight To: Ethan Nelson-Moore Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Russell King , "Russell King (Oracle)" , Arnd Bergmann , Linus Walleij , Kees Cook , Nathan Chancellor , Thomas Weissschuh , Peter Zijlstra , Shubham Bansal , "David S. Miller" Subject: Re: [PATCH] ARM: disable broken eBPF JIT on the Risc PC Message-ID: <20260614125857.398a0e13@pumpkin> In-Reply-To: <20260518014920.135011-1-enelsonmoore@gmail.com> References: <20260518014920.135011-1-enelsonmoore@gmail.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Sun, 17 May 2026 18:49:17 -0700 Ethan Nelson-Moore wrote: > The eBPF JIT unconditionally generates ldrh/strh instructions, which do > not function correctly on the Risc PC because its bus is unable to > signal half-word accesses. Work around this issue by disabling the eBPF > JIT when building for ARMv3 (the Risc PC is the only currently > supported ARMv3 machine). Isn't it more the case that the ldrh/strh instructions were added for armv4. Whether the bus supports 16bit accesses is entirely different. I'm guessing that WRITE_ONCE() gets implemented as two 8-bit writes and the code 'just hopes' than an ISR won't care and won't do an update. David > > Fixes: 39c13c204bb1 ("arm: eBPF JIT compiler") > Cc: stable@vger.kernel.org > Signed-off-by: Ethan Nelson-Moore > --- > arch/arm/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 1155c78bb6aa..8185d013e5d1 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -98,7 +98,7 @@ config ARM > select HAVE_ARCH_TRACEHOOK > select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE > select HAVE_ARM_SMCCC if CPU_V7 > - select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 > + select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 && !CPU_32v3 > select HAVE_CONTEXT_TRACKING_USER > select HAVE_C_RECORDMCOUNT > select HAVE_BUILDTIME_MCOUNT_SORT