From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C31983F23AF for ; Thu, 18 Jun 2026 12:54:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781787299; cv=none; b=I0Z5drKR8PaDNFuuOD882V59M4nwdtn7PAxlwyalKqXhb+kiTH05nZ5UWcu7qaI5yZSkNWd+xTpwHV+knjaiq2a1vw2UhORK1i4wWy4mu0KcZPWiY8evSE02mX7IiIc1C3RkhCyMWbINImxyexjJHzFcV01p3n4vPjn/b8MeY8Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781787299; c=relaxed/simple; bh=Bm4RilFBRvtlQtwGz10vxfNeWX/SAqmCHEJc82RGiyE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mWmWfee5b4Dd1JUVofA1GNHxifj5obDakapejtPkFno7EaAJuSYcJkeWI/+y41W9XZz9+g79SkZ2Aio9bLfxqqgP0JgYgLjlIH5aZaA55Q8t6Aq2R9aVggu8yyafUpG6CzJvsBD5VGIWo/JB/RfHZN2c1T9VB5jLY6TYxy6G9+o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZUU/PY1z; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZUU/PY1z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1F9781F000E9; Thu, 18 Jun 2026 12:54:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781787298; bh=jmP+S9on7Gxn3R7zcanLGoPEnGXWfV4n3XgGRHUL6PI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ZUU/PY1zFA/YY7LR7YEtEfCiQjrtncKMbInusZhfWE3wK/GU3Hxq5nYXUekLhDoQZ t+aDNAfzrYlNaqLdo7Gos9/WbfC5Fz7l7hYcl5SMhk7e13rURxgzNGkeRcGXJudeA1 X/E0StXwFagyWaf5tzg11q7bSTzEtmDv4Ez9ShlDQNDfHDFUCRuy8uJeu9kljJce2L xCGKuM4T2WZi4BlnWHQbmPdopULc+FbWvz/lDmT5ddt0Y5ha2GofeI/3UGAFO4hB8H ygoIUOaFPfKVf5c2kgorvSr79G51RSQ1xFHyHwwbyXus4aaj+uYqB+bJNItOjwDhky EzSqEP5CaJxuw== From: Sasha Levin To: stable@vger.kernel.org Cc: =?UTF-8?q?Ma=C3=ADra=20Canal?= , Jose Maria Casanova Crespo , Iago Toral Quiroga , Sasha Levin Subject: [PATCH 6.12.y 3/3] drm/v3d: Skip CSD when it has zeroed workgroups Date: Thu, 18 Jun 2026 08:54:54 -0400 Message-ID: <20260618125454.649776-3-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260618125454.649776-1-sashal@kernel.org> References: <2026061521-hardship-pebbly-50b5@gregkh> <20260618125454.649776-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Maíra Canal [ Upstream commit 7f93fad5ea0affc9e1505dd0f7596c0fdb496213 ] A compute shader dispatch encodes its workgroup counts in the CFG0..CFG2 registers. Kicking off a dispatch with a zero count in any of the three dimensions is invalid. First, the hardware will process 0 as 65536, while the user-space driver exposes a maximum of 65535. Over that, a submission with a zeroed workgroup dimension should be a no-op. These zeroed counts can reach the dispatch path through an indirect CSD job, whose workgroup counts are only known once the indirect buffer is read and may legitimately be zero, but such scenario should only result in a no-op. Overwrite the indirect CSD job workgroup counts with the indirect BO ones, even if they are zeroed, and don't submit the job to the hardware when any of the workgroup counts is zero, so the job completes immediately instead of running the shader. Cc: stable@vger.kernel.org Fixes: d223f98f0209 ("drm/v3d: Add support for compute shader dispatch.") Suggested-by: Jose Maria Casanova Crespo Reviewed-by: Iago Toral Quiroga Link: https://patch.msgid.link/20260602-v3d-fix-indirect-csd-v4-2-654309e32bc0@igalia.com Signed-off-by: Maíra Canal Signed-off-by: Sasha Levin --- drivers/gpu/drm/v3d/v3d_sched.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/v3d/v3d_sched.c b/drivers/gpu/drm/v3d/v3d_sched.c index f2a2c17a58c687..f2bac920af899d 100644 --- a/drivers/gpu/drm/v3d/v3d_sched.c +++ b/drivers/gpu/drm/v3d/v3d_sched.c @@ -368,6 +368,16 @@ v3d_csd_job_run(struct drm_sched_job *sched_job) return NULL; } + /* The HW interprets a workgroup size of 0 as 65536; however, the + * user-space driver exposes a maximum of 65535. Therefore, a 0 in + * any dimension means that we have no workgroups and the compute + * shader should not be dispatched. + */ + if (!V3D_GET_FIELD(job->args.cfg[0], V3D_CSD_QUEUED_CFG0_NUM_WGS_X) || + !V3D_GET_FIELD(job->args.cfg[1], V3D_CSD_QUEUED_CFG1_NUM_WGS_Y) || + !V3D_GET_FIELD(job->args.cfg[2], V3D_CSD_QUEUED_CFG2_NUM_WGS_Z)) + return NULL; + v3d->queue[V3D_CSD].active_job = &job->base; v3d_invalidate_caches(v3d); @@ -418,13 +428,13 @@ v3d_rewrite_csd_job_wg_counts_from_indirect(struct v3d_cpu_job *job) wg_counts = (uint32_t *)(bo->vaddr + indirect_csd->offset); - if (wg_counts[0] == 0 || wg_counts[1] == 0 || wg_counts[2] == 0) - goto unmap_bo; - args->cfg[0] = wg_counts[0] << V3D_CSD_CFG012_WG_COUNT_SHIFT; args->cfg[1] = wg_counts[1] << V3D_CSD_CFG012_WG_COUNT_SHIFT; args->cfg[2] = wg_counts[2] << V3D_CSD_CFG012_WG_COUNT_SHIFT; + if (wg_counts[0] == 0 || wg_counts[1] == 0 || wg_counts[2] == 0) + goto unmap_bo; + num_batches = DIV_ROUND_UP(indirect_csd->wg_size, 16) * (wg_counts[0] * wg_counts[1] * wg_counts[2]); -- 2.53.0