From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 709843E9588 for ; Thu, 18 Jun 2026 14:13:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781792028; cv=none; b=pMYBdbWL0oiyHeT1fsdh6a6/KbZEkPLFdMd6y+SCRLGo6rHQj2SotHT1oxIRIREmKlJJ+OtoH35myY3QH0xEYBlDx8W5rbq7Ox13lMmLxHCGMy5DO7GleXYeE9oxDmsSJZgPGLhxNh2g9rUUdiXl7MzmPoCc/ZrGiVppL1XvAtE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781792028; c=relaxed/simple; bh=1+gDdmIftQZHRz1xUJIA80OXW0+fsUMvkUfFYTgfW9A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OCkREjRtqQyuyjhCv7YA0RjvhRDo5VPk3WyB1jjJ973UmHpoJXwTeX2zskB5xhFiqDczM3PYMn5pEJ3EinPtLeil3brqwG13l2G2nwrngf3x0ebhj7Yaf/h9R0VEuAo8eh9IWLTpUUk0S2hUI1gK1vOef7FzIFz3QD8Z/7EcVlg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TVhkytjm; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TVhkytjm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BEC131F000E9; Thu, 18 Jun 2026 14:13:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781792027; bh=hJNXYiJ4ne/Dtjiz/6O8TVBXS1tY92r8cXrYxBVsCI4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=TVhkytjmiwK3eAydGk4o++3HUzRblh123xVEpZYeFjm5050rhuxpAsLqOiXIPedPa j24UxeydNJyzdobgGQ3LpZ8roLLOdbs7423Ay+pNk1sSLX1ff3MVeJ0Ks1A18oOVrH 0Vu6yrX9KFn/Z1bhHkK4M3nzeX7usDY9b5NrG6+ULg3iSHerskMFmHFv5jhXezgrUE PQjAN31T+UhTOeoscgsawEFVoO8+MQpyszLvZRWgLYE9mTBpPrlFQzEKbLA1zre2CX 35Ci8REhZ0y57Ie4cdfDwha9VwWQUrkbItiRSILqnbpZQKXAJISVjKdj7RR4fNwd14 ltcHcFejNcuRw== From: Sasha Levin To: stable@vger.kernel.org Cc: =?UTF-8?q?Ma=C3=ADra=20Canal?= , Iago Toral Quiroga , Melissa Wen , Sasha Levin Subject: [PATCH 6.1.y 1/2] drm/v3d: Store the active job inside the queue's state Date: Thu, 18 Jun 2026 10:13:44 -0400 Message-ID: <20260618141345.734343-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026061526-coil-arbitrary-316e@gregkh> References: <2026061526-coil-arbitrary-316e@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Maíra Canal [ Upstream commit 0d3768826d38c0ac740f8b45cd13346630535f2b ] Instead of storing the queue's active job in four different variables, store the active job inside the queue's state. This way, it's possible to access all active jobs using an index based in `enum v3d_queue`. Reviewed-by: Iago Toral Quiroga Reviewed-by: Melissa Wen Link: https://lore.kernel.org/r/20250826-v3d-queue-lock-v3-2-979efc43e490@igalia.com Signed-off-by: Maíra Canal Stable-dep-of: 7f93fad5ea0a ("drm/v3d: Skip CSD when it has zeroed workgroups") Signed-off-by: Sasha Levin --- drivers/gpu/drm/v3d/v3d_drv.h | 8 +++----- drivers/gpu/drm/v3d/v3d_gem.c | 5 +++-- drivers/gpu/drm/v3d/v3d_irq.c | 24 ++++++++++++++---------- drivers/gpu/drm/v3d/v3d_sched.c | 26 ++++++++++++++++++-------- 4 files changed, 38 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/v3d/v3d_drv.h b/drivers/gpu/drm/v3d/v3d_drv.h index a366ea208787df..c1e389635de816 100644 --- a/drivers/gpu/drm/v3d/v3d_drv.h +++ b/drivers/gpu/drm/v3d/v3d_drv.h @@ -26,6 +26,9 @@ struct v3d_queue_state { u64 fence_context; u64 emit_seqno; + + /* Currently active job for this queue */ + struct v3d_job *active_job; }; /* Performance monitor object. The perform lifetime is controlled by userspace @@ -110,11 +113,6 @@ struct v3d_dev { struct work_struct overflow_mem_work; - struct v3d_bin_job *bin_job; - struct v3d_render_job *render_job; - struct v3d_tfu_job *tfu_job; - struct v3d_csd_job *csd_job; - struct v3d_queue_state queue[V3D_MAX_QUEUES]; /* Spinlock used to synchronize the overflow memory diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c index 8b6450a96ebc39..6d5fa39423b24a 100644 --- a/drivers/gpu/drm/v3d/v3d_gem.c +++ b/drivers/gpu/drm/v3d/v3d_gem.c @@ -1115,14 +1115,15 @@ void v3d_gem_destroy(struct drm_device *dev) { struct v3d_dev *v3d = to_v3d_dev(dev); + enum v3d_queue q; v3d_sched_fini(v3d); /* Waiting for jobs to finish would need to be done before * unregistering V3D. */ - WARN_ON(v3d->bin_job); - WARN_ON(v3d->render_job); + for (q = 0; q < V3D_MAX_QUEUES; q++) + WARN_ON(v3d->queue[q].active_job); drm_mm_takedown(&v3d->mm); diff --git a/drivers/gpu/drm/v3d/v3d_irq.c b/drivers/gpu/drm/v3d/v3d_irq.c index 641315dbee8b29..1717504742a665 100644 --- a/drivers/gpu/drm/v3d/v3d_irq.c +++ b/drivers/gpu/drm/v3d/v3d_irq.c @@ -40,6 +40,8 @@ v3d_overflow_mem_work(struct work_struct *work) container_of(work, struct v3d_dev, overflow_mem_work); struct drm_device *dev = &v3d->drm; struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024); + struct v3d_queue_state *queue = &v3d->queue[V3D_BIN]; + struct v3d_bin_job *bin_job; struct drm_gem_object *obj; unsigned long irqflags; @@ -59,13 +61,15 @@ v3d_overflow_mem_work(struct work_struct *work) * some binner pool anyway. */ spin_lock_irqsave(&v3d->job_lock, irqflags); - if (!v3d->bin_job) { + bin_job = (struct v3d_bin_job *)queue->active_job; + + if (!bin_job) { spin_unlock_irqrestore(&v3d->job_lock, irqflags); goto out; } drm_gem_object_get(obj); - list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list); + list_add_tail(&bo->unref_head, &bin_job->render->unref_list); spin_unlock_irqrestore(&v3d->job_lock, irqflags); V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << PAGE_SHIFT); @@ -99,11 +103,11 @@ v3d_irq(int irq, void *arg) if (intsts & V3D_INT_FLDONE) { struct v3d_fence *fence = - to_v3d_fence(v3d->bin_job->base.irq_fence); + to_v3d_fence(v3d->queue[V3D_BIN].active_job->irq_fence); trace_v3d_bcl_irq(&v3d->drm, fence->seqno); - v3d->bin_job = NULL; + v3d->queue[V3D_BIN].active_job = NULL; dma_fence_signal(&fence->base); status = IRQ_HANDLED; @@ -111,11 +115,11 @@ v3d_irq(int irq, void *arg) if (intsts & V3D_INT_FRDONE) { struct v3d_fence *fence = - to_v3d_fence(v3d->render_job->base.irq_fence); + to_v3d_fence(v3d->queue[V3D_RENDER].active_job->irq_fence); trace_v3d_rcl_irq(&v3d->drm, fence->seqno); - v3d->render_job = NULL; + v3d->queue[V3D_RENDER].active_job = NULL; dma_fence_signal(&fence->base); status = IRQ_HANDLED; @@ -123,11 +127,11 @@ v3d_irq(int irq, void *arg) if (intsts & V3D_INT_CSDDONE) { struct v3d_fence *fence = - to_v3d_fence(v3d->csd_job->base.irq_fence); + to_v3d_fence(v3d->queue[V3D_CSD].active_job->irq_fence); trace_v3d_csd_irq(&v3d->drm, fence->seqno); - v3d->csd_job = NULL; + v3d->queue[V3D_CSD].active_job = NULL; dma_fence_signal(&fence->base); status = IRQ_HANDLED; @@ -162,11 +166,11 @@ v3d_hub_irq(int irq, void *arg) if (intsts & V3D_HUB_INT_TFUC) { struct v3d_fence *fence = - to_v3d_fence(v3d->tfu_job->base.irq_fence); + to_v3d_fence(v3d->queue[V3D_TFU].active_job->irq_fence); trace_v3d_tfu_irq(&v3d->drm, fence->seqno); - v3d->tfu_job = NULL; + v3d->queue[V3D_TFU].active_job = NULL; dma_fence_signal(&fence->base); status = IRQ_HANDLED; diff --git a/drivers/gpu/drm/v3d/v3d_sched.c b/drivers/gpu/drm/v3d/v3d_sched.c index 41493cf3d03b81..ff91cdb75bb912 100644 --- a/drivers/gpu/drm/v3d/v3d_sched.c +++ b/drivers/gpu/drm/v3d/v3d_sched.c @@ -80,14 +80,18 @@ static struct dma_fence *v3d_bin_job_run(struct drm_sched_job *sched_job) struct dma_fence *fence; unsigned long irqflags; - if (unlikely(job->base.base.s_fence->finished.error)) + if (unlikely(job->base.base.s_fence->finished.error)) { + spin_lock_irqsave(&v3d->job_lock, irqflags); + v3d->queue[V3D_BIN].active_job = NULL; + spin_unlock_irqrestore(&v3d->job_lock, irqflags); return NULL; + } /* Lock required around bin_job update vs * v3d_overflow_mem_work(). */ spin_lock_irqsave(&v3d->job_lock, irqflags); - v3d->bin_job = job; + v3d->queue[V3D_BIN].active_job = &job->base; /* Clear out the overflow allocation, so we don't * reuse the overflow attached to a previous job. */ @@ -134,10 +138,12 @@ static struct dma_fence *v3d_render_job_run(struct drm_sched_job *sched_job) struct drm_device *dev = &v3d->drm; struct dma_fence *fence; - if (unlikely(job->base.base.s_fence->finished.error)) + if (unlikely(job->base.base.s_fence->finished.error)) { + v3d->queue[V3D_RENDER].active_job = NULL; return NULL; + } - v3d->render_job = job; + v3d->queue[V3D_RENDER].active_job = &job->base; /* Can we avoid this flush? We need to be careful of * scheduling, though -- imagine job0 rendering to texture and @@ -179,10 +185,12 @@ v3d_tfu_job_run(struct drm_sched_job *sched_job) struct drm_device *dev = &v3d->drm; struct dma_fence *fence; - if (unlikely(job->base.base.s_fence->finished.error)) + if (unlikely(job->base.base.s_fence->finished.error)) { + v3d->queue[V3D_TFU].active_job = NULL; return NULL; + } - v3d->tfu_job = job; + v3d->queue[V3D_TFU].active_job = &job->base; fence = v3d_fence_create(v3d, V3D_TFU); if (IS_ERR(fence)) @@ -221,10 +229,12 @@ v3d_csd_job_run(struct drm_sched_job *sched_job) struct dma_fence *fence; int i; - if (unlikely(job->base.base.s_fence->finished.error)) + if (unlikely(job->base.base.s_fence->finished.error)) { + v3d->queue[V3D_CSD].active_job = NULL; return NULL; + } - v3d->csd_job = job; + v3d->queue[V3D_CSD].active_job = &job->base; v3d_invalidate_caches(v3d); -- 2.53.0