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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4926c00a34esm34262945e9.0.2026.06.26.06.53.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2026 06:53:57 -0700 (PDT) Date: Fri, 26 Jun 2026 14:53:56 +0100 From: David Laight To: Linus Walleij Cc: slipher , Nathan Chancellor , Kees Cook , Sami Tolvanen , "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" , "regressions@lists.linux.dev" , "linus.walleij@linaro.org" , "rmk+kernel@armlinux.org.uk" Subject: Re: [REGRESSION] 32-bit ARM's BKPT instruction no longer works Message-ID: <20260626145356.4183d8c5@pumpkin> In-Reply-To: References: X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Fri, 26 Jun 2026 14:53:56 +0200 Linus Walleij wrote: > [Adding Nathan and Kees so we can figure out how best to deal with this] >=20 > On Sun, Jun 21, 2026 at 9:15=E2=80=AFPM slipher = wrote: >=20 > > Consider the C program for 32-bit ARM architectures: > > > > > > int main() { > > __asm__ __volatile__ ("BKPT"); > > return 0; > > } > > > > Expected behavior is that this raises SIGTRAP. Since Linux 6.10 this no > > longer happens; instead execution perpetually resumes at the same > > instruction, using 100% of CPU. It does not matter whether GDB is > > attached. I have tested with an armv7l CPU, but I imagine any other > > variants with the BKPT instruction would be equally affected. > > > > I believe the culprit to be commit > > c3f89986fde7bb9ccc86a901bf28e1f7d69fc3b3 "ARM: 9391/2: hw_breakpoint: > > Handle CFI breakpoints". The commit defines the method-of-entry code 3 > > as "ARM_ENTRY_CFI_BREAKPOINT", but this is the code used for any BKPT > > instruction - see > > https://developer.arm.com/documentation/ddi0379/a/Debug-Register-Refere= nce/Control-and-status-registers/Debug-Status-and-Control-Register--DSCR-?l= ang=3Den > > "Method of Debug Entry (MOE), bits [5:2]". If the CFI option is disabled > > in the kernel config, hw_breakpoint_pending() returns 0 indicating the > > breakpoint was handled, but takes no action. So breakpoints cannot be > > used by user-space code, regardless of how CONFIG_CFI is set. The blog > > post > > https://www.jwhitham.org/2015/04/the-mystery-of-fifteen-millisecond.html > > gives a nice overview of the control flow in older, working kernels. =20 >=20 > Does simply reverting the patch solve the issue? >=20 > > The following Systemtap script can be used to demonstrate that the > > ARM_ENTRY_CFI_BREAKPOINT path is used, when running the above C program= . =20 >=20 > Yeah it's definitely that one causing it. >=20 > I sent the naive solution to it, and before anyone point it out: no it do= es > not allow custom breakpoints to be mixed with kernel CFI, but it > probably makes legacy systems work on newer kernels since they > probably don't select CFI. > https://lore.kernel.org/linux-arm-kernel/20260626-arm32-cfi-bug-v1-1-a467= b5050c0b@kernel.org/T/#u >=20 > I understand that this is not solving everything. I'm confused. Why would building a kernel with CFI (to check kernel indirect calls) change the behaviour of executing anything in userspace? If userspace is compiled with CFI and gets an equivalent fail then you'd (probably) want a fatal signal - but isn't that entirely unrelated to the kernel code. Do those checks even need kernel support? I know shadow stacks do. David >=20 > If it is under all circumstances unacceptable to be able to construct > a userspace which will change the user-facing behaviour of BKPT, > I think we need to revert CFI breakpoint handling, back put the patch, > disable CFI on ARM and wait for the compiler(s) to start behaving > differently on ARM. >=20 > CFI folks: any ideas on what we could do instead of BKPT > when we hit a CFI snag? Any ideas from other architectures? >=20 > Yours, > Linus Walleij >=20