From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18C0A4749CE for ; Wed, 22 Jul 2026 18:00:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784743253; cv=none; b=uWJB40/AResEh16xW+w1oZ8yBbQqxdkC+fr9PrXAkcIfPOSuFkw2b7Nj7Wihtyq7Pvj8l2RvrTDUA0ZEm42/Q9HO7qIgrSEDDIrgYB4aQLCCVGdo/PHNOuZjiZrPMwf145p8HK5v2meFvzIFY5nQV5X4KkxdDk8pDVHMGXczyPY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784743253; c=relaxed/simple; bh=My+Yh22XTHyLeE97IbcxFfExgnwazFSjDJkMVZE7N2o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MV8mY+Hk0tNDv4yTKL/QfAwwAtnkTGGOGGnCsmU2Um7K7YiUINrN1ebZLHNkz6ffZd7KbD64uMbUCuD9InhomYkDoYQSmffLILCSlUc5Ep6fckKxIMYtt2eKKG2nUdpw4qtpigmaO3MWP15mDzyFVQqt4DlNDZG4/t+f1LZlWqM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=diX2j7H3; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="diX2j7H3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2B8781F00A3E; Wed, 22 Jul 2026 18:00:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784743251; bh=piPwnS1u+W9bezhRjRjNv7Ahjhj8Q+gBTQIJ8YNVeFo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=diX2j7H34OUMtXqT+63ON6c7hX34QhDbkZzLHFAjRISHXbk52HDkB7987fmI5oWaM dykoHxjsjmwpsV3fSRcQMNFGJLc/Yq488dZJwmwV/OUCtCjGaH9eUhFKjucZiOuMOQ RenHaod4YUGU/Puab+j5aIEbRLLwMOQiv7Tf0suzMAXpZ72xTBJOEdGW+SZxSZeoCU KOtcp3fewA2Z+n7DLx3yK012qDZJSTeru3YBVP7ScZnlJ6sjIHu7DzmCdZyasc9DOS 1dWh9ff6gyfz5v4WEfaQY6Eyzc/TaKiGb+crfLwobWRtffWS0i7qoYjiW5GpfcUQPz CjJE9BzdA/Ztw== From: Sasha Levin To: stable@vger.kernel.org Cc: Abel Vesa , Dmitry Baryshkov , Konrad Dybcio , Bjorn Andersson , Sasha Levin Subject: [PATCH 6.18.y 2/2] arm64: dts: qcom: hamoa: Fix OPP tables for all DisplayPort controllers Date: Wed, 22 Jul 2026 14:00:48 -0400 Message-ID: <20260722180048.2184180-2-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260722180048.2184180-1-sashal@kernel.org> References: <2026072016-discern-gooey-8e42@gregkh> <20260722180048.2184180-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Abel Vesa [ Upstream commit c17e220946675232d383620ed9cff6685735ec48 ] According to internal documentation, the corners specific for each rate from the DP link clock are: - LOWSVS_D1 -> 19.2 MHz - LOWSVS -> 270 MHz - SVS -> 540 MHz (594 MHz in case of DP3) - SVS_L1 -> 594 MHz - NOM -> 810 MHz - NOM_L1 -> 810 MHz - TURBO -> 810 MHz So fix all tables for each of the four controllers according to the documentation, but since DP0 through DP2 have the same entries in their tables, lets drop the DP1 and DP2 and have all of them share the DP0 table instead. However keep a separate table for the DP3 as it is different for the SVS, compared to the rest of the controllers. The 19.2 MHz @ LOWSVS_D1 isn't needed as it's not an actual working frequency and the controller will never select it. So remove it. Cc: stable@vger.kernel.org # v6.9+ Fixes: 1940c25eaa63 ("arm64: dts: qcom: x1e80100: Add display nodes") Suggested-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260323-hamoa-fix-dp3-opp-table-v3-1-a823776bd1b0@oss.qualcomm.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 77 ++++---------------------- 1 file changed, 12 insertions(+), 65 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 062911cc208322..adb18c10dbd9fe 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5522,18 +5522,18 @@ mdss_dp0_out: endpoint { mdss_dp0_opp_table: opp-table { compatible = "operating-points-v2"; - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - opp-270000000 { opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; + required-opps = <&rpmhpd_opp_low_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; @@ -5574,7 +5574,7 @@ mdss_dp1: displayport-controller@ae98000 { <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - operating-points-v2 = <&mdss_dp1_opp_table>; + operating-points-v2 = <&mdss_dp0_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -5606,30 +5606,6 @@ mdss_dp1_out: endpoint { }; }; }; - - mdss_dp1_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; }; mdss_dp2: displayport-controller@ae9a000 { @@ -5662,7 +5638,7 @@ mdss_dp2: displayport-controller@ae9a000 { <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - operating-points-v2 = <&mdss_dp2_opp_table>; + operating-points-v2 = <&mdss_dp0_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -5693,30 +5669,6 @@ mdss_dp2_out: endpoint { }; }; }; - - mdss_dp2_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; }; mdss_dp3: displayport-controller@aea0000 { @@ -5779,19 +5731,14 @@ mdss_dp3_out: endpoint { mdss_dp3_opp_table: opp-table { compatible = "operating-points-v2"; - opp-162000000 { - opp-hz = /bits/ 64 <162000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - opp-270000000 { opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; + required-opps = <&rpmhpd_opp_low_svs>; }; - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + required-opps = <&rpmhpd_opp_svs>; }; opp-810000000 { -- 2.53.0