From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8C72352014 for ; Mon, 3 Aug 2026 23:26:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785799575; cv=none; b=Luu4hEXUQ0eIWQWdFiZJvEcmAWiPchyelHn9ITkSz7hVaTP5RQ2Ro9b2fp8KT0mhvQI/t7UV2b4HhzDXoJCWwREN9KbDVyXSJwKaxZdWi+MUC+yQpwIa2HWG7Qy2kzinAON/zNNNTFMEWseEYFf54eiW0lJu5SbMLdSf6gAEKss= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785799575; c=relaxed/simple; bh=PNajYqjZC34yYyANf6uKioJE7ekOi1G+BwQYWeiCdkI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JsaxsEcy00YUPau0lcVvkdgp0gG1BnO1m4Hejl/hFllxjZfsAI/KEMI8lgaqe/UPgl5v0H/ttl/IwmQHZ1MQpkdKzVC85HZQ55yoqAfSYUTDQQb8bWFgu/PeoYtPmk3Hx6ZH92PJLCSq+66nRRrhr8HhtDCijRooTAzHSJbKxok= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=D01HBjMu; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="D01HBjMu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785799573; x=1817335573; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PNajYqjZC34yYyANf6uKioJE7ekOi1G+BwQYWeiCdkI=; b=D01HBjMudXqBtjBLxyYrEqtETarPeGf6PmTYpcoqgOlHPWPovjPABv85 WQL5LZ3eUe3rPNyrrhkZ2Yv+hS4d+1Xee1MaxRdk6OFAHJWlWJyM2FclW CasBbObLNRNl49bmr1ObntEvAMq3c1lCFqA145Rise+K/JcRxxWOyvwh0 p1XfnSubGnGEkivdFtoxj1Sbnaf1ptkWirdIdgIbrzqxdVc+6G6+vXG9C VsyEX0oZCwBmglyu/J7OoBiCO5ke82I9J9SB4oZOp3Bi1z4LFErYdSDST tk7NwsjZ6v/9y+vnu6QDYUDzqSqaifsTAAwB4rbYSUu/+Em/7q8c8ddC1 w==; X-CSE-ConnectionGUID: HLuy8aSxQ+60bNhV4thYOw== X-CSE-MsgGUID: xueQnbUJT7aulOXGGf7C2Q== X-IronPort-AV: E=McAfee;i="6800,10657,11864"; a="90232404" X-IronPort-AV: E=Sophos;i="6.25,203,1779174000"; d="scan'208";a="90232404" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2026 16:26:12 -0700 X-CSE-ConnectionGUID: GXZNs0BpSISEF+Q4L8zdrA== X-CSE-MsgGUID: d2B/cjslRre2ZXSp5geh9A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,203,1779174000"; d="scan'208";a="261932551" Received: from orsosgc001.jf.intel.com ([10.88.27.185]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2026 16:26:12 -0700 From: Ashutosh Dixit To: stable@vger.kernel.org Cc: Sasha Levin , Greg Kroah-Hartman Subject: [PATCH 6.18.y 01/10] drm/xe/rtp: Refactor OAG MMIO trigger register whitelisting Date: Mon, 3 Aug 2026 16:25:59 -0700 Message-ID: <20260803232608.3276045-2-ashutosh.dixit@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260803232608.3276045-1-ashutosh.dixit@intel.com> References: <20260803232608.3276045-1-ashutosh.dixit@intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit [ Upstream commit ed455775c5a68b75e5f6ad6c8e0e3e9c98fd3f64 ] Minor refactor of OAG MMIO trigger register whitelisting for code reuse with OAM MMIO trigger register whitelisting. Signed-off-by: Ashutosh Dixit Reviewed-by: Umesh Nerlige Ramappa Link: https://patch.msgid.link/20251202025115.373546-5-ashutosh.dixit@intel.com --- drivers/gpu/drm/xe/xe_reg_whitelist.c | 29 ++++++++++++--------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c index 21763dc51150b..47fb3e74b567c 100644 --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c @@ -66,27 +66,24 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { ENGINE_CLASS(RENDER)), XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0)) }, - { XE_RTP_NAME("oa_reg_render"), + +#define WHITELIST_OA_MMIO_TRG(trg, status, head) \ + WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \ + WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \ + WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4) + +#define WHITELIST_OAG_MMIO_TRG \ + WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR) + + { XE_RTP_NAME("oag_mmio_trg_rcs"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER, - RING_FORCE_TO_NONPRIV_ACCESS_RW), - WHITELIST(OAG_OASTATUS, - RING_FORCE_TO_NONPRIV_ACCESS_RD), - WHITELIST(OAG_OAHEADPTR, - RING_FORCE_TO_NONPRIV_ACCESS_RD | - RING_FORCE_TO_NONPRIV_RANGE_4)) + XE_RTP_ACTIONS(WHITELIST_OAG_MMIO_TRG) }, - { XE_RTP_NAME("oa_reg_compute"), + { XE_RTP_NAME("oag_mmio_trg_ccs"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED), ENGINE_CLASS(COMPUTE)), - XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER, - RING_FORCE_TO_NONPRIV_ACCESS_RW), - WHITELIST(OAG_OASTATUS, - RING_FORCE_TO_NONPRIV_ACCESS_RD), - WHITELIST(OAG_OAHEADPTR, - RING_FORCE_TO_NONPRIV_ACCESS_RD | - RING_FORCE_TO_NONPRIV_RANGE_4)) + XE_RTP_ACTIONS(WHITELIST_OAG_MMIO_TRG) }, }; -- 2.54.0