From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 961ED395AC0 for ; Mon, 3 Aug 2026 23:26:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785799579; cv=none; b=e2KCGyUWITRqJXRH2+mW2BVaZuJcPoHNXVAfcSKfvt30Lmt/vkgULKt3opSzMnxBb8nfii//OZF3cOo3BJMz8WLs9R2d64MKJzmmFMKzt/agBJfdWMNl0IQPkbRAvqFDYXJ3hTpk960ZO55fyClAZo0F8s6hfdNqMJ98KZ6jDGA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785799579; c=relaxed/simple; bh=sn0+mYq/Wmala77HTxZ9QyS/4La59BxZ1bBy0FPA3XI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bhmox/wsNCEqUsB7qt5DKUJoULidQk4cEtKcrFCEY04o6usXVscpTUlOGdjfM9smcKPlo8FEvVNF2DuCsIB/pBEBaEj5DhvzTQkwDpQwVyIgg26Txlzu0xzMaEr/hM3c/JANo5ewnh6bMn9Ceg3yx+3ttPLJB7Ku48PNGx5VYsY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kQTIwCzN; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kQTIwCzN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785799577; x=1817335577; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sn0+mYq/Wmala77HTxZ9QyS/4La59BxZ1bBy0FPA3XI=; b=kQTIwCzNpIS+hfTkNM00xQLJ8vsRApKwHBGHgw++FPNYVI6nK4X11vQO Vx2QrRYTCm78FfaDNhF9IM6Y0WgK4JJ7Y1+8M1gYEtyDEypNHc+VJe+pt T7ooLH08ATSwYUXXXqUaQN8a1fwhdcSbHd6ad6o2OiuT7FNTtgpd/ql8O Tz5j8SGZ2mK/KQGcTdDQCI8K9c0D+OxWCUdKywnR6JlBgBy4HwxHZ9OeH sGXWMDKaOGWt+8oMjt6yYoctV7gLACATP1go316PSCuEDFqR12YpjohWu cAxPgEZPzmMdC7ksYlY3/nt8Vus4DoBa+V0ZvZSRIznZo4a/bWhL8ERSt g==; X-CSE-ConnectionGUID: v9j32ReIQIeG7PhxrztlFA== X-CSE-MsgGUID: xoIqx1nGTDyURA5S4vb8+Q== X-IronPort-AV: E=McAfee;i="6800,10657,11864"; a="90232410" X-IronPort-AV: E=Sophos;i="6.25,203,1779174000"; d="scan'208";a="90232410" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2026 16:26:12 -0700 X-CSE-ConnectionGUID: texYL0ekTBSFV/X/4F2rUw== X-CSE-MsgGUID: H2ZD3pirR5KjcMq9WqZJAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,203,1779174000"; d="scan'208";a="261932553" Received: from orsosgc001.jf.intel.com ([10.88.27.185]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2026 16:26:13 -0700 From: Ashutosh Dixit To: stable@vger.kernel.org Cc: Sasha Levin , Greg Kroah-Hartman Subject: [PATCH 6.18.y 03/10] drm/xe/rtp: Maintain OA whitelists separately Date: Mon, 3 Aug 2026 16:26:01 -0700 Message-ID: <20260803232608.3276045-4-ashutosh.dixit@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260803232608.3276045-1-ashutosh.dixit@intel.com> References: <20260803232608.3276045-1-ashutosh.dixit@intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit [ Upstream commit c478244a9e2d14b3f1f92e8bd293919e554622a5 ] Contains minor modification of the above commit because of changed API. OA registers are dynamically whitelisted (and again dewhitelisted) on OA stream open/close. Maintaining OA whitelists separately from non-OA register whitlists simplifies this management of OA register whitelisting/dewhitelisting. Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") Cc: stable@vger.kernel.org # v6.12+ Signed-off-by: Ashutosh Dixit Reviewed-by: Umesh Nerlige Ramappa Link: https://patch.msgid.link/20260615224227.34880-3-ashutosh.dixit@intel.com --- drivers/gpu/drm/xe/xe_gt_debugfs.c | 4 +++- drivers/gpu/drm/xe/xe_hw_engine.c | 2 ++ drivers/gpu/drm/xe/xe_hw_engine_types.h | 8 ++++++++ drivers/gpu/drm/xe/xe_reg_whitelist.c | 6 ++++++ 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c index f253e2df49077..1a4d8d4f44b4d 100644 --- a/drivers/gpu/drm/xe/xe_gt_debugfs.c +++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c @@ -174,8 +174,10 @@ static int register_save_restore(struct xe_gt *gt, struct drm_printer *p) drm_printf(p, "\n"); drm_printf(p, "Whitelist\n"); - for_each_hw_engine(hwe, gt, id) + for_each_hw_engine(hwe, gt, id) { xe_reg_whitelist_dump(&hwe->reg_whitelist, p); + xe_reg_whitelist_dump(&hwe->oa_whitelist, p); + } xe_pm_runtime_put(gt_to_xe(gt)); diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index d88770370eeb0..66a738f17a3ba 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -565,6 +565,8 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe, hw_engine_setup_default_state(hwe); xe_reg_sr_init(&hwe->reg_whitelist, hwe->name, gt_to_xe(gt)); + xe_reg_sr_init(&hwe->oa_whitelist, hwe->name, gt_to_xe(gt)); + xe_reg_sr_init(&hwe->oa_sr, hwe->name, gt_to_xe(gt)); xe_reg_whitelist_process_engine(hwe); } diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h index e4191a7a2c318..04ca7545d22c3 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h @@ -128,6 +128,14 @@ struct xe_hw_engine { * @reg_whitelist: table with registers to be whitelisted */ struct xe_reg_sr reg_whitelist; + /** + * @oa_whitelist: oa registers to be whitelisted + */ + struct xe_reg_sr oa_whitelist; + /** + * @oa_sr: oa nonpriv whitelist registers, changed on oa stream open/close + */ + struct xe_reg_sr oa_sr; /** * @reg_lrc: LRC workaround registers */ diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c index 5cb7e0e3a66bd..6b7c90ba6d10c 100644 --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c @@ -66,6 +66,9 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { ENGINE_CLASS(RENDER)), XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0)) }, +}; + +static const struct xe_rtp_entry_sr oa_whitelist[] = { #define WHITELIST_DENY(r, f) WHITELIST(r, (f) | RING_FORCE_TO_NONPRIV_DENY) @@ -138,6 +141,9 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist), &hwe->reg_whitelist); whitelist_apply_to_hwe(hwe); + + xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist), + &hwe->oa_whitelist); } /** -- 2.54.0