From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F4AF453A50 for ; Mon, 24 Aug 2026 16:52:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787590342; cv=none; b=ihfwHJwB/ceHvvNwbgvRa2qRoG5wMdI/z+iP4DvIfAYTKGgXnAklUlgNrhE2eXcZleS3+L5tfe1TkU2mFa3Xi7YvH7pWfFil0f9VRxQsP6xXl6AXiBgSiALsx5260VjfY0Gtcl6q1eFdm8bmOMuoBpXigKcdpETRDboKW5mYyuE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787590342; c=relaxed/simple; bh=BhOPZgim9vP/lkp4DSODeJnpt/PstxUuZqpzq3V5NcU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uuh4B46h937vedabpGSjuGg/bBm+OKjkUBYB2+Sn6YMJ3yWZcVD3ZNBmIrDhsIbd7zyk6Wwi6vHPXtX43BuvyR7whmqsa3guj3AgsyVI15p16JsDVNVsjrWrU+oSEzL4jXhov7iMfMDozwVwjR9lqBLq3RkKpp2m6SYNOC70t94= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VEfdGi7d; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VEfdGi7d" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787590340; x=1819126340; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BhOPZgim9vP/lkp4DSODeJnpt/PstxUuZqpzq3V5NcU=; b=VEfdGi7dOPJ6aJUjld7Q31/9Od6iSxtjnZbJ4yMqzbz2OCuFycXkNlRx DuMrQi0COTZugJ0zOUhigTK6wFOCAVKHLABFL0ixbhG7m0BdThuLRRvzj Tatz68qIKdEfSsgWfD1RDgWS6noV0LlTk9/iIkrMEYIpetCr6VZi5eeEu XGoBuCaNYsu53+c7H8IWB4oiLg+oUCdDsnE2GCwdOTd8uADQF5JrniakX E/paAyD995bbdyNugAempCJNs8vqN1iI25VeqipjwGfRLS9RgAOZq7vbd H2zcrv+nJ5B/Ry1gRePsxmVsNumk7t5xtIboP2nUSDMpwafRM2Y0t5Xf6 A==; X-CSE-ConnectionGUID: uMjXiijFRrm49ICLIO7xmA== X-CSE-MsgGUID: TSrt9fPqQzOS2JgJwqxnEA== X-IronPort-AV: E=McAfee;i="6800,10657,11885"; a="98723381" X-IronPort-AV: E=Sophos;i="6.25,241,1779174000"; d="scan'208";a="98723381" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2026 09:52:19 -0700 X-CSE-ConnectionGUID: mZYzuZLaTcK4pnZjQ/YXBg== X-CSE-MsgGUID: wnnqsKRaRziDKlnHwd+2+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,241,1779174000"; d="scan'208";a="268995295" Received: from dut6094bmgfrd.fm.intel.com ([10.80.55.39]) by fmviesa004.fm.intel.com with ESMTP; 24 Aug 2026 09:52:18 -0700 From: Jia Yao To: stable@vger.kernel.org Cc: Jia Yao , Gwan-gyeong Mun , Matthew Auld , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= Subject: [PATCH 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX Date: Mon, 24 Aug 2026 16:52:07 +0000 Message-ID: <20260824165208.498797-2-jia.yao@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824165208.498797-1-jia.yao@intel.com> References: <2026082036-afterglow-tapered-84a0@gregkh> <20260824165208.498797-1-jia.yao@intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On iGPU, the UM queue BO is allocated in system memory. On dGFX, the BO was previously created in system memory and later reallocated in xe_guc_realloc_post_hwconfig(). Allocate the UM queue BO directly in VRAM on dGFX, where it is ultimately required. Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement") Cc: Gwan-gyeong Mun Cc: Matthew Auld Cc: # v6.12+ Signed-off-by: Jia Yao Reviewed-by: Matthew Auld Signed-off-by: Matthew Auld Link: https://patch.msgid.link/20260804165057.129529-3-jia.yao@intel.com (cherry picked from commit ace076ef0a854ab5940bacc539bf66afd61d118c) Signed-off-by: Thomas Hellström (cherry picked from commit f342810a141f8a7e8b3786a6e4b6c0695a078a74) --- drivers/gpu/drm/xe/xe_guc.c | 6 ------ drivers/gpu/drm/xe/xe_guc_ads.c | 8 +++++--- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c index cc5741f751b9..ae0c88da422b 100644 --- a/drivers/gpu/drm/xe/xe_guc.c +++ b/drivers/gpu/drm/xe/xe_guc.c @@ -700,12 +700,6 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc) if (ret) return ret; - if (guc->ads.um_queue_bo) { - ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo); - if (ret) - return ret; - } - return 0; } diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c index 806c2618a7cd..4c3e21b5e60e 100644 --- a/drivers/gpu/drm/xe/xe_guc_ads.c +++ b/drivers/gpu/drm/xe/xe_guc_ads.c @@ -392,15 +392,17 @@ int xe_guc_ads_init(struct xe_guc_ads *ads) /* * Allocate a separate BO for the HW fault ring (UM queues). * - * Round the size up to the next power of two so that + * Round the size up to the next power of two so that on iGPU * (system memory, no IOMMU) the TTM pool issues a single * alloc_pages(order=N) call, maximising the chance of getting * a physically contiguous block. GuC requires contiguous DPA. */ - size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE * + size_t um_size = IS_DGFX(xe) ? + GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX : + roundup_pow_of_two(GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX); - u32 um_flags = XE_BO_FLAG_SYSTEM | + u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | XE_BO_FLAG_GGTT | XE_BO_FLAG_GGTT_INVALIDATE | XE_BO_FLAG_PINNED_NORESTORE; -- 2.43.0