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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cee5d476esm2206255e9.1.2026.09.02.09.07.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 09:07:05 -0700 (PDT) Date: Wed, 2 Sep 2026 17:07:05 +0100 From: David Laight To: Christoph Hellwig Cc: Eric Biggers , Andrew Morton , linux-raid@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, stable@vger.kernel.org Subject: Re: [PATCH RESEND] xor: add missing vzeroupper to AVX code Message-ID: <20260902170705.213d432d@pumpkin> In-Reply-To: <20260902133706.GA21538@lst.de> References: <20260831212248.213805-1-ebiggers@kernel.org> <20260902133706.GA21538@lst.de> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 2 Sep 2026 15:37:06 +0200 Christoph Hellwig wrote: > On Mon, Aug 31, 2026 at 02:22:48PM -0700, Eric Biggers wrote: > > Since the AVX optimized XOR code uses YMM registers, execute vzeroupper > > before returning from it. This is needed to avoid degrading the > > performance of any later SSE code that may happen to be executed. > > > > Fixes: ea4d26ae24e5 ("raid5: add AVX optimized RAID5 checksumming") > > Cc: stable@vger.kernel.org > > Signed-off-by: Eric Biggers > > --- > > > > This didn't get taken through the x86 tree. Andrew, it seems you're > > taking patches to lib/raid/. Can you apply this one? > > Can we do kernel_avx_{begin,end} instead of having to open code > and document this everywhere, please? In which case I think you want the vzeroupper in kernel_avx_begin(). Actually, for some cpu at least, you need vzeroupper in kernel_fpu_begin() even if the code only uses the SSE registers. See: https://stackoverflow.com/questions/41303780/why-is-this-sse-code-6-times-slower-without-vzeroupper-on-skylake Basically, on Skylake, all SSE hit a penalty if any ymm high bits might be non-zero. Don't know what has changed since... I don't have the Intel optimisation manual downloaded (ok, I might have it but have NFI where), and the link on that page is broken. David