From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E085545D82; Wed, 9 Sep 2026 13:56:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788962171; cv=none; b=WOtihkP9Ang7vnx+kCvIjIyqSHTg9t9jk/Ffeb9X4YYzuC9dDSuA2/6xKnZzdiLmzjCj2hg3R5EiENh1XsV/U8mU3WaM7pbLR/xWDQ4hMU9SJJE5hcnjEdnKd2pU9LfsZw9TvrdI7OjgLbgo7KaemUm+86+1gZPIPM9G5LG2e+Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788962171; c=relaxed/simple; bh=37Ny3Bm2SnP+d8Yj6nqDdZt1AZDU3DN4l0R8wMTqENY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uXvwP+dsRI6QZwlbF/vn+q/oHU8N6RhyWhVqo36Jj13ohVXQq8W8nkXtUHj/Z4E8aryAbFTTF3JzO3vQ3/4h0NWbbWLS4rMveCKW2pYDT2c3iJF49bcL4Sgo12yK1cW1JATiLkN9PM84MwqfeMh4s35ei5zrKwgxxcEitNlzL3k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=rdOCJpdD; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="rdOCJpdD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9744F1F00A3A; Wed, 9 Sep 2026 13:56:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1788962170; bh=4GGX9StCs86tJqidZ5HnI1i1Zg087beOdJq+LHcjROY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=rdOCJpdDyMHVhgUq/THhnLuild99so8oH/ZhLY/T83jglmvQzN77HV7R9j4OPouTE EAsoU4XJ076quSe1HYY1MY5jG5KIyS6W9INqu1BvXnXP2i3YjdvF/8gKnIFb0NNMRy BRQXsQuQAcJyvtdp2npnEpdAjVtgAnKgx+dSMyEM= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, James Hilliard , Miquel Raynal Subject: [PATCH 7.2 197/556] mtd: rawnand: sunxi: describe tADL and tWHR delays Date: Wed, 9 Sep 2026 15:37:57 +0200 Message-ID: <20260909134237.332184429@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260909134230.441546314@linuxfoundation.org> References: <20260909134230.441546314@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 7.2-stable review patch. If anyone has any objections, please let me know. ------------------ From: James Hilliard commit 147f2a5743f8864bfc265654b1856af11c8c0031 upstream. The tADL and tWHR timing fields use four encoded delays, but the driver currently derives their values with a shift. This hides the actual controller timing characteristics and lets the clock solver select a 32-cycle delay that the fields cannot encode. Describe the legacy 7, 15, 23 and 31 cycle thresholds explicitly and use the tables for both clock selection and field lookup. This prepares the driver for controllers with different encodings. Fixes: 88fd4e4deae8 ("mtd: rawnand: sunxi: Add support for H616 nand controller") Cc: stable@vger.kernel.org Signed-off-by: James Hilliard Signed-off-by: Miquel Raynal Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/nand/raw/sunxi_nand.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -242,6 +242,8 @@ struct sunxi_nand_hw_ecc { /* Delay arrays contain internal NDFC clock cycles for field values 0 to 3. */ struct sunxi_nfc_timings { s32 tWB[SUNXI_NFC_TIMING_STEPS]; + s32 tADL[SUNXI_NFC_TIMING_STEPS]; + s32 tWHR[SUNXI_NFC_TIMING_STEPS]; s32 tRHW[SUNXI_NFC_TIMING_STEPS]; }; @@ -1679,6 +1681,8 @@ static int sunxi_nfc_hw_ecc_write_oob(st static const struct sunxi_nfc_timings sun4i_a10_nfc_timings = { .tWB = { 6, 12, 16, 20 }, + .tADL = { 7, 15, 23, 31 }, + .tWHR = { 7, 15, 23, 31 }, .tRHW = { 4, 8, 12, 20 }, }; @@ -1781,11 +1785,15 @@ static int sunxi_nfc_setup_interface(str min_clk_period = DIV_ROUND_UP(timings->tWB_max, nfc_timings->tWB[SUNXI_NFC_TIMING_STEPS - 1]); - if (timings->tADL_min > (min_clk_period * 32)) - min_clk_period = DIV_ROUND_UP(timings->tADL_min, 32); - - if (timings->tWHR_min > (min_clk_period * 32)) - min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32); + if (timings->tADL_min > + (min_clk_period * nfc_timings->tADL[SUNXI_NFC_TIMING_STEPS - 1])) + min_clk_period = DIV_ROUND_UP(timings->tADL_min, + nfc_timings->tADL[SUNXI_NFC_TIMING_STEPS - 1]); + + if (timings->tWHR_min > + (min_clk_period * nfc_timings->tWHR[SUNXI_NFC_TIMING_STEPS - 1])) + min_clk_period = DIV_ROUND_UP(timings->tWHR_min, + nfc_timings->tWHR[SUNXI_NFC_TIMING_STEPS - 1]); if (timings->tRHW_min > (min_clk_period * nfc_timings->tRHW[SUNXI_NFC_TIMING_STEPS - 1])) @@ -1813,16 +1821,18 @@ static int sunxi_nfc_setup_interface(str return tWB; } - tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3; - if (tADL > 3) { + tADL = sunxi_nand_lookup_timing(nfc_timings->tADL, + timings->tADL_min, min_clk_period); + if (tADL < 0) { dev_err(nfc->dev, "unsupported tADL\n"); - return -EINVAL; + return tADL; } - tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3; - if (tWHR > 3) { + tWHR = sunxi_nand_lookup_timing(nfc_timings->tWHR, + timings->tWHR_min, min_clk_period); + if (tWHR < 0) { dev_err(nfc->dev, "unsupported tWHR\n"); - return -EINVAL; + return tWHR; } tRHW = sunxi_nand_lookup_timing(nfc_timings->tRHW, timings->tRHW_min,