From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CE25351C2A for ; Sat, 12 Sep 2026 14:21:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789222873; cv=none; b=PmYws2LMkeP6SYHv2kfgw8mtehIKVoSt1vtHRWl6PPikiO16aI+9WSB+F9oqv3MPX7L8Fl6pkD5R9n8tePGeJ5T1RLI3KOtmEvclwhOu9Q9JyiJ1SuMkO7NxPqAnRc7fOycwH8wSOG0DHk29PaIAQHFOn1tqJNaVXaabO8dvPgA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789222873; c=relaxed/simple; bh=iRhBMlGBrCf8Me0T/05luk+3rOuc70pcFfzSDqK6wYE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tO22Itas1/51cW4kHmfb2rMW2jtJlXrTB8x399uyBLfbk1DEX/JWa2b30sA/ZoF4a7x2IuAOHAKdx4+Q988bh8B9yeYZ/T4qld1aACSWPXsuPDp6SEwn3oD5jFT3DlLTdejJkUvY3QkwFECR11K/BsiWV0Hdfd89oWY4n99Fz8I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cPfe2jgc; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cPfe2jgc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BCA411F00899; Sat, 12 Sep 2026 14:21:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789222872; bh=aXjVtQc2FnS6V7F6QcHA7juQoBNznN7wjSk7W2Mx7c8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=cPfe2jgctIfavwl+6THDVNlcIdNvAVkYC6x8AaWw6e8TxEE8e2Q0oX7s9c1ejpOAz WhwFvCkZ29Br/yEWVKNhUQomOWgUvthNmt4ZkVx5MQXe2QRrvEiedWczNcCdrUcRJ6 CKUl2v0E4m7e7hjDkSmtUtAzZ+Xc87tB3+51EJuf+nIJvOL4slE39dDcyT8Sn6lgY4 PkqIS8O6Z5taY1IsTVsd4IxAct3cInf55zwYu9ynSEQ5cey/n7yn2DShSpKixZYbq7 BtbCYTVk5TaPrm94QNva2FMXoGRQeVOB573HTGwfPpciPmTC/chYyX5XUOmuBVn8rY 0AOUESuM/pEiQ== From: Sasha Levin To: stable@vger.kernel.org Cc: Nemesa Garg , =?UTF-8?q?Jouni=20H=C3=B6gander?= , Animesh Manna , Jani Nikula , Sasha Levin Subject: [PATCH 6.18.y] drm/i915/display: Clear SEL_FETCH_PLANE_CTL on plane disable Date: Sat, 12 Sep 2026 10:21:10 -0400 Message-ID: <20260912142110.2914999-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026090953-dander-coat-86af@gregkh> References: <2026090953-dander-coat-86af@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Nemesa Garg [ Upstream commit 7f1172a2ac0d7e50850785e2e65789c8aac8411a ] icl_plane_disable_sel_fetch_arm() wrote SEL_FETCH_PLANE_CTL = 0 only when crtc_state->enable_psr2_sel_fetch was set. If a plane was disabled after selective fetch had been turned off, the guard fired early and left the register's enable bit set in hardware. The bit is harmless until selective fetch is re-enabled. When it is, the hardware resumes fetching for the now-disabled plane and keeps its old DDB range reserved. i9xx_cursor_disable_sel_fetch_arm() has the same guard on SEL_FETCH_CUR_CTL and is fixed the same way. v2: Add same check for cursor also. [sashiko] Cc: stable@vger.kernel.org Fixes: b1f5279b5981 ("drm/i915/psr: Move plane sel fetch configuration into plane source files") Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8739 Assisted-by: GitHub-Copilot:claude-opus-4.6 Signed-off-by: Nemesa Garg Reviewed-by: Jouni Högander Signed-off-by: Animesh Manna Link: https://patch.msgid.link/20260818095149.2172935-1-nemesa.garg@intel.com (cherry picked from commit 600a7c9d40e5e0c5544f42d1c9592c8d15224dc0) Signed-off-by: Jani Nikula [ Adjusted context for missing pixel-normalizer code in icl_plane_disable_arm(). ] Signed-off-by: Sasha Levin --- drivers/gpu/drm/i915/display/intel_cursor.c | 15 ++++++++++----- .../gpu/drm/i915/display/skl_universal_plane.c | 15 ++++++++++----- 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index d4d181f9dca5f..1734127eee269 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -530,13 +530,18 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, } static void i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb, - struct intel_plane *plane, - const struct intel_crtc_state *crtc_state) + struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; - if (!crtc_state->enable_psr2_sel_fetch) + /* + * Clear this whenever the hardware has selective fetch, not just when + * the current state uses it. The cursor may have been enabled with + * selective fetch earlier and had its enable bit orphaned when the + * feature was switched off. + */ + if (!HAS_PSR2_SEL_FETCH(display)) return; intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0); @@ -586,7 +591,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_dsb *dsb, if (crtc_state->enable_psr2_su_region_et) wa_16021440873(dsb, plane, crtc_state, plane_state); else - i9xx_cursor_disable_sel_fetch_arm(dsb, plane, crtc_state); + i9xx_cursor_disable_sel_fetch_arm(dsb, plane); } } @@ -695,7 +700,7 @@ static void i9xx_cursor_update_arm(struct intel_dsb *dsb, if (plane_state) i9xx_cursor_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state); else - i9xx_cursor_disable_sel_fetch_arm(dsb, plane, crtc_state); + i9xx_cursor_disable_sel_fetch_arm(dsb, plane); if (plane->cursor.base != base || plane->cursor.size != fbc_ctl || diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index e13fb781e7b20..e01a494b9eafa 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -886,13 +886,18 @@ skl_plane_disable_arm(struct intel_dsb *dsb, } static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb, - struct intel_plane *plane, - const struct intel_crtc_state *crtc_state) + struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; - if (!crtc_state->enable_psr2_sel_fetch) + /* + * Clear this whenever the hardware has selective fetch, not just when + * the current state uses it. The plane may have been enabled with + * selective fetch earlier and had its enable bit orphaned when the + * feature was switched off. + */ + if (!HAS_PSR2_SEL_FETCH(display)) return; intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0); @@ -912,7 +917,7 @@ icl_plane_disable_arm(struct intel_dsb *dsb, skl_write_plane_wm(dsb, plane, crtc_state); - icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state); + icl_plane_disable_sel_fetch_arm(dsb, plane); intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0); intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0); } @@ -1613,7 +1618,7 @@ static void icl_plane_update_sel_fetch_arm(struct intel_dsb *dsb, intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), SEL_FETCH_PLANE_CTL_ENABLE); else - icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state); + icl_plane_disable_sel_fetch_arm(dsb, plane); } static void -- 2.53.0