From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5592A48643C for ; Mon, 5 Oct 2026 13:49:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791208157; cv=none; b=SnQDwJcJN2/mf0qopi2rKfmLYtTRuj7CcTj+ylNUahjWPvn90B8wkOnJG6llN9/AXo/qDV9jWEZaDMnITsGl2koujCR4sI/b41Me/k5DNQfy39rjKrx04HIFfvHOkePI3gqMs2FS4udXOZyQeDOfduQpLJG+46KXpX+xmoVwAdI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791208157; c=relaxed/simple; bh=HWx7tRwef77gGudYXamT+zO1JSgKYruUuZCPppRxRCc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fY25MO587Swb6gnYkegJw8ld1l9l5kdRXilbCmtEECrDArAwBY2kLKQJ5+dTho4d9Lovz0T5lKZRbHmACUPNzUe2MskSuvb7d8VsoYRQBifrax29HjYHSU4xaIGawDy6bJjPEkO28XLMLCkuZHhbuYebEJCCQWQZpM2usxf8gYA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=adQUyHky; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="adQUyHky" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B62341F000FF; Mon, 5 Oct 2026 13:49:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1791208156; bh=wzNflc4rzMI0CduciR4m0CibA1S5dp4nH57cFfYXrEs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=adQUyHkyZ5kN/Lg5u6hITjXMklAwazOdtpbGHt6HS8tqHPHyepBMql1dx+Ke/MXWd jpZfFD6IYtJsFvvqRNErgaN7yJw9MBkZcDrxQ+ajbv6da5vPGRB9wm6yqivoPkxpay bS5JrU3UKXdYb6hphJ0NEBF5t7befIA5fCHFUNcp6RRqn2m9D01a+lElQiohfXXALb yqlJsPjgjGxwVV3fVy3oarSvoKrnRz3R/SQwpOYfMWOd9w9J0F90j+ozY+oBYRmBtI 8wGolek35VRYl6OKHMLTJyqa2e6SlE5ILAPdV9zkcoi3+bmGP9ohfLmmdcnUw7CwRZ eQWKRKIpw3Irg== From: Sasha Levin To: stable@vger.kernel.org Cc: =?UTF-8?q?Timur=20Krist=C3=B3f?= , Mario Limonciello , Alex Deucher , Sasha Levin Subject: [PATCH 5.10.y] drm/amd/pm/si: Fix updating clock limits on AC/DC Date: Mon, 5 Oct 2026 09:49:12 -0400 Message-ID: <20261005134720.2686534-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026100545-equipment-natural-a359@gregkh> References: <2026100545-equipment-natural-a359@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Timur Kristóf [ Upstream commit 08c9100f65299c64439e22e6057d750ae0e6c660 ] Assume that the AC limits are the maximum of all power states, and the DC limits are the maximum of battery power states. This shouldn't make any difference in practice, but is cleaner and more robust against bogus information in the VBIOS. Fixes: e6c5d36756e7 ("drm/amd/pm/si: Fix updating clock limits from power states") Signed-off-by: Timur Kristóf Reviewed-by: Mario Limonciello Link: https://patch.msgid.link/20260923120354.1027996-2-timur.kristof@gmail.com Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher (cherry picked from commit ef8cb9dcc7db7b7abcbdbe870a080cc81e4f0bf3) Cc: stable@vger.kernel.org Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/pm/powerplay/si_dpm.c | 36 +++++++++++------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c index f4bb4d2c3f77b..f142e51b21221 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c @@ -7135,6 +7135,19 @@ static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev, adev->pm.dpm.uvd_ps = rps; } +static void si_update_limits(struct amdgpu_clock_and_voltage_limits *limits, + struct rv7xx_pl *pl) +{ + if (pl->sclk > limits->sclk) + limits->sclk = pl->sclk; + if (pl->mclk > limits->mclk) + limits->mclk = pl->mclk; + if (pl->vddc > limits->vddc) + limits->vddc = pl->vddc; + if (pl->vddci > limits->vddci) + limits->vddci = pl->vddci; +} + static void si_parse_pplib_clock_info(struct amdgpu_device *adev, struct amdgpu_ps *rps, int index, union pplib_clock_info *clock_info) @@ -7143,7 +7156,6 @@ static void si_parse_pplib_clock_info(struct amdgpu_device *adev, struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); struct si_power_info *si_pi = si_get_pi(adev); struct si_ps *ps = si_get_ps(rps); - struct amdgpu_clock_and_voltage_limits *limits; u16 leakage_voltage; struct rv7xx_pl *pl = &ps->performance_levels[index]; int ret; @@ -7208,26 +7220,14 @@ static void si_parse_pplib_clock_info(struct amdgpu_device *adev, * VBIOS can contain conflicting values between: * - the maximum allowed clocks and voltages on AC or DC * - the clocks and voltages in power states on AC or DC + * + * Assume that the AC limits are the maximum of all power states, + * and the DC limits are the maximum of battery power states. */ + si_update_limits(&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac, pl); if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == - ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) - limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; - else if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) - limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; - else - limits = NULL; - - if (limits) { - if (pl->sclk > limits->sclk) - limits->sclk = pl->sclk; - if (pl->mclk > limits->mclk) - limits->mclk = pl->mclk; - if (pl->vddc > limits->vddc) - limits->vddc = pl->vddc; - if (pl->vddci > limits->vddci) - limits->vddci = pl->vddci; - } + si_update_limits(&adev->pm.dpm.dyn_state.max_clock_voltage_on_dc, pl); } union pplib_power_state { -- 2.53.0