From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 013D1412BF3 for ; Mon, 5 Oct 2026 22:53:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791240819; cv=none; b=IINogtI9apI1LYLypGtn9lEXkmrshZDo6wHFRVlvlRI+9aL2Aca/syjqHdW3oDwVq3wNyciKl03Y7QM0GUBIdNqTywzHpcB86OSlm6oGKmLW64gyaR53S9cDgvFil1Nt5Rbo3sxE+DomY8zuYuu+hq16Y8DtB6hWOVmzJOmIbSo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791240819; c=relaxed/simple; bh=5ZE3ibuEAfRpvP/mVGFvj8MJ9tmZ3uBmJ3J9fCXiSnQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VG11KC4J/e042zvqYUDd4OKLwvnwMTyUIZU7D1/RwK7uyhPYKWvDtm0CtRS7FAMrHP/OiBbiurZoy4dFtAhnhXRWFujXGVAtWKqUPGnueR0xyTuy+N1vdxuwPcfJ6snlWhiPS7y45ZMzflA3Ev2Q/qRElGkzs2Rq9uGxOGgM/mo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=V1Y/hmvl; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="V1Y/hmvl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5565E1F000FF; Mon, 5 Oct 2026 22:53:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1791240817; bh=9RCIhV8ca/HteepAA9wSjELRe0ev7SJfnmc8yP4Ttxs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=V1Y/hmvlWn9yA08eDIb5Gi9G4C1TWVqLp/qn2lrUAP2ft2T5SnY/itqbONGnrlJNf NwruaC0yfTmygeaWoZ4cmCEW5+wWSuYO/I+ANjKcx2AfRkXXY3T0umTv/gMEACL8X2 b+xXt0mINhVWeevEnEbz6G87lxkVJttx3DWQPwdmiitig1N3flkcwTsTt0bh96frTC K+sMtFq0NGfuzJvPLgIcQ7WndyBrautbhqAzvWkXHyPdP0iyIubWLH9ZSfNVnFXZ2s WM4BVApUjvfsjiGOZozsWNvnlKTfvEItjleNo5y2PRaeZdzXstulGea6GdwTPvrN1x Cj/BHrgIfzA/w== From: Sasha Levin To: stable@vger.kernel.org Cc: Beata Michalska , Vladimir Murzin , Will Deacon , Sasha Levin Subject: [PATCH 7.2.y 1/2] arm64: errata: Factor out broken AMU const counter cap Date: Mon, 5 Oct 2026 18:53:33 -0400 Message-ID: <20261005225325.3487067-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026100500-widget-handcart-8d85@gregkh> References: <2026100500-widget-handcart-8d85@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Beata Michalska [ Upstream commit 573371caf7aea8582212da81dcead2c3f48fac4b ] Move the workaround from the erratum 2457168-specific cpucap to a generic broken AMU constant-counter one. This keeps the existing Cortex-A510 handling unchanged while allowing other errata with similar AMU constant counter issue to share the capability bit and call sites. Signed-off-by: Beata Michalska Reviewed-by: Vladimir Murzin Signed-off-by: Will Deacon Omit the comment update in amu_read_core_const_ctrs(), since paired CPPC FFH counter reads are not implemented here. Keep the capability rename in the existing counter-read and initialization paths, together with the shared MIDR range list needed by the additional erratum. Stable-dep-of: 45f730467987 ("arm64: errata: Add Cortex-A725 erratum 3821522 workaround") Signed-off-by: Sasha Levin --- arch/arm64/Kconfig | 8 ++++++++ arch/arm64/kernel/cpu_errata.c | 20 ++++++++++++++------ arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kernel/topology.c | 2 +- arch/arm64/tools/cpucaps | 2 +- 5 files changed, 25 insertions(+), 9 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fc57d90d92c1d..a38a3940cf208 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1017,9 +1017,17 @@ config ARM64_ERRATUM_1902691 If unsure, say Y. +config ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + bool + # Targeting errata affecting AMEVCNTR01, the AMU constant counter. + # On affected CPUs the counter may not increment at the expected rate, + # making it unreliable. As a result, AMU users should treat it as + # unavailable rather than relying on misleading counter values. + config ARM64_ERRATUM_2457168 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT default y help This option adds the workaround for ARM Cortex-A510 erratum 2457168. diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index be47908bb9d22..a6dc9f20373e5 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -377,6 +377,16 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { }; #endif +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT +static const struct midr_range workaround_amu_constcnt_list[] = { +#ifdef CONFIG_ARM64_ERRATUM_2457168 + /* Cortex-A510 r0p0-r1p1 */ + MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), +#endif + {} +}; +#endif /* CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT */ + #ifdef CONFIG_CAVIUM_ERRATUM_23154 static const struct midr_range cavium_erratum_23154_cpus[] = { MIDR_ALL_VERSIONS(MIDR_THUNDERX), @@ -904,14 +914,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) }, #endif -#ifdef CONFIG_ARM64_ERRATUM_2457168 +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT { - .desc = "ARM erratum 2457168", - .capability = ARM64_WORKAROUND_2457168, + .desc = "Broken AMU AMEVCNTR01 (const counter)", + .capability = ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT, .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, - - /* Cortex-A510 r0p0-r1p1 */ - CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) + CAP_MIDR_RANGE_LIST(workaround_amu_constcnt_list) }, #endif #ifdef CONFIG_ARM64_ERRATUM_2038923 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 103e70d683ca2..5dbc20d6d9694 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2087,7 +2087,7 @@ static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) cpumask_set_cpu(smp_processor_id(), &amu_cpus); /* 0 reference values signal broken/disabled counters */ - if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) + if (!this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT)) update_freq_counters_refs(); } } diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index a0d5870bcb657..15035f051c25b 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -390,7 +390,7 @@ static void cpu_read_constcnt(void *val) * the counter is disabled. A return value of 0 at counter read is * properly handled as an error case by the users of the counter. */ - *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_2457168) ? + *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT) ? 0UL : read_constcnt(); } diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 9b85a84f6fd49..050175dfa3240 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -103,7 +103,6 @@ WORKAROUND_1902691 WORKAROUND_2038923 WORKAROUND_2064142 WORKAROUND_2077057 -WORKAROUND_2457168 WORKAROUND_2645198 WORKAROUND_2658417 WORKAROUND_4193714 @@ -128,3 +127,4 @@ WORKAROUND_REPEAT_TLBI WORKAROUND_SPECULATIVE_AT WORKAROUND_SPECULATIVE_SSBS WORKAROUND_SPECULATIVE_UNPRIV_LOAD +WORKAROUND_BROKEN_AMU_CONSTCNT -- 2.53.0