From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62CAD1E505 for ; Tue, 6 Oct 2026 00:29:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791246593; cv=none; b=mY2ecER6lSl55OOS6ZTkF0RUxjL0OwdVfNHxmJyaWp6Mic1kHwvaW5Up2rDfv1Wo7jabVF0Xa7ARUhuJP18IUlLfYiaN8c5Mt7zpG9katcz7/GpKjkR5nkDnePRn6oEmB3P8mzBtrSIX28zLNT/ZVh87O1X1Trs71KBawt8C7jg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791246593; c=relaxed/simple; bh=DmDf4dSo10nOdOfFeV0/kB/2xK5Cry23NJRCLnoDYhY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=i6dcCWg7ttrpfXt+kVFmEowbX1gIQn4trKO+F1kgfkLkOeReceZPtbrtH3615JYmqyunij0jLb83fjbnfKmdaoxChBQmiCbRNMp5uZjsDU9j2gfTELfC0fOqhdAmfjsoPRK2skbyjk70Oj5u/BuBkIc3e5TASvhS85ijfvwS2gc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Y+CydilR; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Y+CydilR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C26051F000FF; Tue, 6 Oct 2026 00:29:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1791246592; bh=VDEkQD8/yu34I+KVu1aiwrSw8BwSTbpCY54xP5QQvkY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Y+CydilRhOBrj+JTnshRYcniK+1i7NhIDEe21GeMGC3V1p7CGpaK70/eF5Ijo9JHi F4xjdNxq+vHudF2acQ8Njr3aKovAcoLmjHvnZI1VtMlvjoDSsXaDBxeGg2IeHIcPBT 3k0ZNQoDyz2CbT5ncSRnmr237Shu1i2f/tDPoSYUs0l/P4GsFVoIOBAtzpDl+DIezg c7OxBCJK05pt1jpheD/xiLP50KdD715iQb/tWTjWQYfuQL7PQgwYDG12+uPoQBpEZO bmqMKshm+j7ICGzezZCK1xMHiBV42bmuZ2+sywbI6yxaEir2F0Ut/eklB450mm4+wz K7UN+S7oIRlhQ== From: Sasha Levin To: stable@vger.kernel.org Cc: Beata Michalska , Vladimir Murzin , Will Deacon , Sasha Levin Subject: [PATCH 6.12.y 1/2] arm64: errata: Factor out broken AMU const counter cap Date: Mon, 5 Oct 2026 20:29:47 -0400 Message-ID: <20261006002934.3618253-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026100501-unsubtle-blank-50b6@gregkh> References: <2026100501-unsubtle-blank-50b6@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Beata Michalska [ Upstream commit 573371caf7aea8582212da81dcead2c3f48fac4b ] Move the workaround from the erratum 2457168-specific cpucap to a generic broken AMU constant-counter one. This keeps the existing Cortex-A510 handling unchanged while allowing other errata with similar AMU constant counter issue to share the capability bit and call sites. Signed-off-by: Beata Michalska Reviewed-by: Vladimir Murzin Signed-off-by: Will Deacon Omit the comment-only update to the paired AMU counter reader, which is absent here. Retain the shared capability, CPU matching list, and the checks in the existing counter-read and frequency-invariance paths. Stable-dep-of: 45f730467987 ("arm64: errata: Add Cortex-A725 erratum 3821522 workaround") Signed-off-by: Sasha Levin --- arch/arm64/Kconfig | 8 ++++++++ arch/arm64/kernel/cpu_errata.c | 20 ++++++++++++++------ arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kernel/topology.c | 2 +- arch/arm64/tools/cpucaps | 2 +- 5 files changed, 25 insertions(+), 9 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 938bf2f96b1a8..d2901607b4f9e 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1023,9 +1023,17 @@ config ARM64_ERRATUM_1902691 If unsure, say Y. +config ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + bool + # Targeting errata affecting AMEVCNTR01, the AMU constant counter. + # On affected CPUs the counter may not increment at the expected rate, + # making it unreliable. As a result, AMU users should treat it as + # unavailable rather than relying on misleading counter values. + config ARM64_ERRATUM_2457168 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT default y help This option adds the workaround for ARM Cortex-A510 erratum 2457168. diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 80e47d3e86af4..1dc2373fc1b9c 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -259,6 +259,16 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { }; #endif +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT +static const struct midr_range workaround_amu_constcnt_list[] = { +#ifdef CONFIG_ARM64_ERRATUM_2457168 + /* Cortex-A510 r0p0-r1p1 */ + MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), +#endif + {} +}; +#endif /* CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT */ + #ifdef CONFIG_CAVIUM_ERRATUM_23154 static const struct midr_range cavium_erratum_23154_cpus[] = { MIDR_ALL_VERSIONS(MIDR_THUNDERX), @@ -750,14 +760,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) }, #endif -#ifdef CONFIG_ARM64_ERRATUM_2457168 +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT { - .desc = "ARM erratum 2457168", - .capability = ARM64_WORKAROUND_2457168, + .desc = "Broken AMU AMEVCNTR01 (const counter)", + .capability = ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT, .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, - - /* Cortex-A510 r0p0-r1p1 */ - CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) + CAP_MIDR_RANGE_LIST(workaround_amu_constcnt_list) }, #endif #ifdef CONFIG_ARM64_ERRATUM_2038923 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 8246015fd2d73..ae4782ce523a6 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2070,7 +2070,7 @@ static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) cpumask_set_cpu(smp_processor_id(), &amu_cpus); /* 0 reference values signal broken/disabled counters */ - if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) + if (!this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT)) update_freq_counters_refs(); } } diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index cb180684d10d5..d21b4e963f6b7 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -271,7 +271,7 @@ static void cpu_read_constcnt(void *val) * the counter is disabled. A return value of 0 at counter read is * properly handled as an error case by the users of the counter. */ - *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_2457168) ? + *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT) ? 0UL : read_constcnt(); } diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index eedb5acc21ed9..edb2e35e5e7ee 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -85,7 +85,6 @@ WORKAROUND_1902691 WORKAROUND_2038923 WORKAROUND_2064142 WORKAROUND_2077057 -WORKAROUND_2457168 WORKAROUND_2645198 WORKAROUND_2658417 WORKAROUND_AMPERE_AC03_CPU_38 @@ -105,3 +104,4 @@ WORKAROUND_REPEAT_TLBI WORKAROUND_SPECULATIVE_AT WORKAROUND_SPECULATIVE_SSBS WORKAROUND_SPECULATIVE_UNPRIV_LOAD +WORKAROUND_BROKEN_AMU_CONSTCNT -- 2.53.0