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Mon, 12 Oct 2026 10:01:44 -0700 (PDT) From: Magnus Lindholm To: Imre Kaloz Cc: bhelgaas@google.com, linux-pci@vger.kernel.org, andreas@gaisler.com, sparclinux@vger.kernel.org, davem@davemloft.net, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Magnus Lindholm Subject: Re: [PATCH] PCI: Avoid D3 on PLX PEX 8532/8533/8548 downstream ports Date: Mon, 12 Oct 2026 19:00:57 +0200 Message-ID: <20261012170113.985649-1-linmag7@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260927105609.8813-1-kaloz@kernel.org> References: <20260927105609.8813-1-kaloz@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Imre, Tested this on a Sun Ultra 45 with PLX PEX8532 downstream ports and an LSI SAS1064 controller. Without the patch, enabling CONFIG_PCIEPORTBUS reproducibly causes a Cheetah bus-error panic when mptbase probes the controller. The kernel boots with pcie_port_pm=off. With this patch, the same kernel and config boot successfully without pcie_port_pm=off or pcie_ports=compat. The quirk is applied to all five PEX8532 downstream ports, the LSISAS1064 initializes, and the modular mptsas/ext4 setup boots through the initramfs normally. Tested-by: Magnus Lindholm