From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794047675; b=h1p8F+fq3b8dzra9g3DB6xicJFfPU03IF+riE4oVJVtmnjqFOrac6cgxjVO0fVMOcmW0 HS5Ad8mBoLbRqrJHUxOgtQlSF2mHdBoYn1MoIURfCD34Z721ifg8BX92V66FHXWCpEuR/ sSgBlvMVdK6czr9j88oElgPUJCJfPPbeOrLTcpCENDFMOQI24MlDEYtqGwSI3k6nu0IO/ 6viBRqvfi3Jn+7aQTg/pOnp6lVA5aNPGZZmXel1cN0fGYOMeKuRQxGNaO8CdAZ6ZZvpFw /2e6OvQpfh0vUFxrN6Gm/0vRSZ/LpeYiYaKXXystP1EcKfAz0NPTQpTLg61x7jtKLqA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794047675; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: MIME-Version:Content-Type:Content-Transfer-Encoding; bh=0aL+BmwWJ4AF+PYQA7B2hpdPVhtJbj+EEE/c3DumJhU=; b=scl0RwgUjTbQiyyPJC02BNtRoQV79bIGFjlASXMqT4Nj7EiRFd9YU62apvQh81El2/3O wmau5Vp11VueVfdEBLREEGduTgOQQlKYHoLfZ6ZSaOCUBFrjX2DWWH+yWvAnEPlxBXFmC 79z819XJ41hzj+VAbOLv2z+ydU92VFhXPNGbxkJrHmCrfeRdB+aBw1pE0vxCz6HXlvLbU G4ax2n7ecD1UeVCxSCTTgacr7XdWnqT8D/ys6mdXgBb8Y4Y3cxKrXM0ivfkxtI3cvkwlD kBoZXA3B8PdSYeXQdO2H3DA6gR5rZLQC6LviagMg5h9NarO8uJSUSPdjmcQ6CDRwglw== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=Qg+WkKZV; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BFF7606A326 for ; Sat, 7 Nov 2026 10:34:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=Qg+WkKZV Received: by smtp.kernel.org (Postfix) with ESMTPSA id CE3521F0089F; Sat, 7 Nov 2026 10:34:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1794047674; bh=0aL+BmwWJ4AF+PYQA7B2hpdPVhtJbj+EEE/c3DumJhU=; h=From:To:Cc:Subject:Date; b=Qg+WkKZVuo3hvgttpMJVEC0oaPRmFOUELdQ132W2+QpQxuKBxbmkfAwGDf8hWDuHd BJQot8QqNZhCg35PctNVUYbqk2oDfbyQ/VZgCnNFJYMYX7KC2sd81VH3NIjBid7Qz4 GRUaGQWLLGL6RoEidgS2yHgV2G60Fzf6eGxZj0C9vz5Ags3T7fTT+wEeM44H2iuPlq WF/VLwZZlraJdAEH9HJ2zy7negw2tvlkfkBYpXvAu20RdWe/BmyvmO+GB6LDq5NMMh cx6Glo+BHLeTasTisV0ZopwypoxdjqnIMiU+rkIO33Gp3v1eVkJ6CSy4EhUexJXi3u 3JyZkgwDD8cTw== From: Sasha Levin To: geraldogabriel@gmail.com, dsimic@manjaro.org, shawn.lin@rock-chips.com, manivannan.sadhasivam@oss.qualcomm.com, bhelgaas@google.com Cc: stable@vger.kernel.org Subject: FAILED: patch "[PATCH] PCI: rockchip: Drive at 2.5 GT/s, error other speeds" failed to apply to 6.6-stable tree Date: Sat, 7 Nov 2026 05:34:32 -0500 Message-ID: <20261107053432-failed-6.6-84d08ff902f1@kernel.org> X-Mailer: git-send-email 2.53.0 X-Mailing-List: stable@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The patch below does not apply to the 6.6-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.6.y git checkout FETCH_HEAD git cherry-pick -x 84d08ff902f1ec01177fef1a21a38934927f5aee # git commit -s git send-email --to '' --in-reply-to '20261107053432-failed-6.6-84d08ff902f1@kernel.org' --subject-prefix 'PATCH 6.6.y' 'HEAD^..' Thanks, Sasha ------------------ original commit in Linus's tree ------------------ >From 84d08ff902f1ec01177fef1a21a38934927f5aee Mon Sep 17 00:00:00 2001 From: Geraldo Nascimento Date: Tue, 16 Jun 2026 12:26:10 -0300 Subject: [PATCH] PCI: rockchip: Drive at 2.5 GT/s, error other speeds Configure the core to be driven at 2.5 GT/s Link Speed and ignore any other speed with a warning. Also drop the 5.0 GT/s Link Speed defines from Rockchip PCIe header. The reason is that Shawn Lin from Rockchip has reiterated that there may be danger of "catastrophic failure" in using their PCIe with 5.0 GT/s speeds. While Rockchip has done so informally without issuing a proper errata, and the particulars are thus unknown, this may cause data loss or worse. This change is corroborated by RK3399 official datasheet [1], which states maximum link speed for this platform is 2.5 GT/s. [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver") Reported-by: Dragan Simic Reported-by: Shawn Lin Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/ Signed-off-by: Geraldo Nascimento Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Reviewed-by: Dragan Simic Reviewed-by: Shawn Lin Cc: stable@vger.kernel.org Link: https://patch.msgid.link/7421df7a7b7778ee99363cccfdfabbfa8aa6ab5e.1781622998.git.geraldogabriel@gmail.com --- drivers/pci/controller/pcie-rockchip.c | 14 ++++++-------- drivers/pci/controller/pcie-rockchip.h | 3 --- 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index 8d78ab1b31f0f..45cc888ac5537 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -66,8 +66,10 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) } rockchip->link_gen = of_pci_get_max_link_speed(node); - if (rockchip->link_gen < 0 || rockchip->link_gen > 2) - rockchip->link_gen = 2; + if (rockchip->link_gen < 0 || rockchip->link_gen >= 2) { + rockchip->link_gen = 1; + dev_warn(dev, "invalid max-link-speed, limited to 2.5 GT/s\n"); + } for (i = 0; i < ROCKCHIP_NUM_PM_RSTS; i++) rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i]; @@ -147,12 +149,8 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) goto err_exit_phy; } - if (rockchip->link_gen == 2) - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, - PCIE_CLIENT_CONFIG); - else - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, - PCIE_CLIENT_CONFIG); + rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, + PCIE_CLIENT_CONFIG); regs = PCIE_CLIENT_ARI_ENABLE | PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 3e82a69b9c006..b5da15601b585 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -42,7 +42,6 @@ #define PCIE_CLIENT_MODE_RC HWORD_SET_BIT(0x0040) #define PCIE_CLIENT_MODE_EP HWORD_CLR_BIT(0x0040) #define PCIE_CLIENT_GEN_SEL_1 HWORD_CLR_BIT(0x0080) -#define PCIE_CLIENT_GEN_SEL_2 HWORD_SET_BIT(0x0080) #define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c) #define PCIE_CLIENT_INT_IN_ASSERT HWORD_SET_BIT(0x0002) #define PCIE_CLIENT_INT_IN_DEASSERT HWORD_CLR_BIT(0x0002) @@ -197,8 +196,6 @@ (((x) & PCIE_CORE_PL_CONF_LS_MASK) == PCIE_CORE_PL_CONF_LS_READY) #define PCIE_LINK_UP(x) \ (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP) -#define PCIE_LINK_IS_GEN2(x) \ - (((x) & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) #define RC_REGION_0_ADDR_TRANS_H 0x00000000 #define RC_REGION_0_ADDR_TRANS_L 0x00000000 -- 2.53.0