From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794050580; b=EGFmjXvhsGSEiuL46KBNiO7y04JtzFzcYmM3/4LeeatVL34gEwIXdcnVFCHiBP2LpMoJ iFGbRn80CXSI6mR1yg38GK9/rK+8WwgzAQrz7yzRv1pnuExugAYusZHSh5Ri7otjh1VXM 8DFBrulVrR6/sZlHaJjcMEVh13Wbx4DuFjkcDLXNtfrHbDA8HBzWJrE+YZcoZGfr5y9B1 tuHv8mjJltC1EBJI8h3ZXQbmCHoeDsUH96Xb4dKQDOix6fYPLlJLSqkcfZPoni98lFsKG wqheo26WoqEhrHmkxM43rDTVUQS3xodzOmClnu0dTV8md1HDJNlG21vcMkHAPrN5udg== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794050580; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: MIME-Version:Content-Type:Content-Transfer-Encoding; bh=8r8mMvmdbAHdRX8hnsjX+n42spbs0nbPga/URgu4u6Y=; b=zh9BvD8W/ydzV6SX/6mVNUr7FpRDn3vJKS9HwEYiArq48nkPVJ0pa0ni8gFktoepQdTP ffrXrJO6BV45gVgXY40uwvmpmP+8Cdc08Y4/YRVMIXHbyN4oBDsJrUvpQArUQIJidkFKE O2wMsed/lY5f/X9EANPaBL6wY4dOWIU5vmJrilDgmLGtrfL9CwAGRW00UzXDSLuD8ChED pXfHOcLykeoWZtYDNfVFwYuBRJ5Rc3fyWx/zOHMeWENPt4lZB7xQyDSTJ6IryLBV2ilYK 0NWv0buLOzi96QAoBH5OjbhaikiO6GA1mXr9FWVt/Nu8mzvx4shwYDwCb3hqj632kHQ== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=Cu+HTTjb; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E6DF606A326 for ; Sat, 7 Nov 2026 11:23:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=Cu+HTTjb Received: by smtp.kernel.org (Postfix) with ESMTPSA id C1EC51F0089F; Sat, 7 Nov 2026 11:22:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1794050580; bh=8r8mMvmdbAHdRX8hnsjX+n42spbs0nbPga/URgu4u6Y=; h=From:To:Cc:Subject:Date; b=Cu+HTTjbWo92Dh8wQQ9j27ekAGeBWdtuugd8Z7UnQ7BoNc5xvVnWkpDzq317oR6rb 2qhhoyjBgblPKVu8DtQMgeiQDrDhjI9E+18Ou38v8z62fa0mWbZn+E1ijAuYiDauhY sRh1edwiDvnNS35SCcQ3DoROagK3DHpPbC9O8ova3OHA9VI4mxc+DiuigRYj+cWrHU 0veUNjD/bjmkZJimQMr0z4cH7Hw+B7rtIvCZeg4O+ortgfdvfw4VFS4VPM24SFz3W2 ZqSJrmVcdKwtk1DbHO0VUdvTbTJ97xI09kScEWFmHvGWLtMeQs7fWGkR9OtMldXe9i e8mDzYZ47njMQ== From: Sasha Levin To: kmehltretter@gmail.com, bigeasy@linutronix.de, rmk+kernel@armlinux.org.uk Cc: stable@vger.kernel.org Subject: FAILED: patch "[PATCH] ARM: 9521/1: cacheinfo: count external caches in early_cache_level()" failed to apply to 5.10-stable tree Date: Sat, 7 Nov 2026 06:22:58 -0500 Message-ID: <20261107062258-failed-5.10-4fd69e8a9ebc@kernel.org> X-Mailer: git-send-email 2.53.0 X-Mailing-List: stable@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The patch below does not apply to the 5.10-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-5.10.y git checkout FETCH_HEAD git cherry-pick -x 4fd69e8a9ebc42e292637ec2ebfb6bcf2d2f6c0e # git commit -s git send-email --to '' --in-reply-to '20261107062258-failed-5.10-4fd69e8a9ebc@kernel.org' --subject-prefix 'PATCH 5.10.y' 'HEAD^..' Thanks, Sasha ------------------ original commit in Linus's tree ------------------ >From 4fd69e8a9ebc42e292637ec2ebfb6bcf2d2f6c0e Mon Sep 17 00:00:00 2001 From: Karl Mehltretter Date: Mon, 21 Sep 2026 21:44:33 +0100 Subject: [PATCH] ARM: 9521/1: cacheinfo: count external caches in early_cache_level() early_cache_level() counts only caches described by CLIDR. An external PL310 is absent from CLIDR, and its arm,pl310-cache compatible is not accepted by init_of_cache_level(), so early allocation falls back to an incomplete count. init_cache_level() later adds the DT-described L2, forcing reallocation on the secondary CPU with interrupts disabled. This defeats early allocation on PREEMPT_RT. Use init_cache_level() for early sizing too, so the initial allocation includes external caches described by the device tree. Assisted-by: LLM Cc: stable@vger.kernel.org Tested-by: Sebastian Andrzej Siewior Link: https://lore.kernel.org/r/20260912195552.76673-3-kmehltretter@gmail.com/ Signed-off-by: Karl Mehltretter Signed-off-by: Russell King --- arch/arm/kernel/cacheinfo.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/arm/kernel/cacheinfo.c b/arch/arm/kernel/cacheinfo.c index 860eeb03cfe5d..31591c9472548 100644 --- a/arch/arm/kernel/cacheinfo.c +++ b/arch/arm/kernel/cacheinfo.c @@ -111,13 +111,6 @@ static int detect_cache_level(unsigned int *level_p, unsigned int *leaves_p) return 0; } -int early_cache_level(unsigned int cpu) -{ - struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); - - return detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves); -} - int init_cache_level(unsigned int cpu) { unsigned int level, leaves; @@ -146,6 +139,11 @@ int init_cache_level(unsigned int cpu) return 0; } +int early_cache_level(unsigned int cpu) +{ + return init_cache_level(cpu); +} + int populate_cache_leaves(unsigned int cpu) { unsigned int level, idx; -- 2.53.0