From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794061451; b=hjoetFL4uCfPW5MWxOTiCQHY76hWeOS3M7p4yIIvVvxqR0piQ0/XLuWEmJm2p+yFAmOb 8uoHTgl8OYVZwLn4K1L7LNrGP6DbzjPJ+97DXuaFU6qoF8ZGuabhKUvHValBGARAPVqky bKAzEX4KDnFF6ddHbiG8gPAQD66re4MCqKh4XIynggmkWqpodZqsf1m5Ot4yTjmci6FFy fSwnE5ZrCUN4EgneRBRD04LgbGLU0YZAz1AkxZdKAcrvPAuJQ9goKBDTkJG6XgIoNcmuB PTyQOuXuhZgt9wEvsGLVXZOWnCsX9/fg00CSW57pBu4tpnHIY1h7BYgisH3cr7TVzrA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794061451; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:User-Agent:X-stable:X-Patchwork-Hint: MIME-Version:Content-Transfer-Encoding; bh=+ywgtp4ISDzmojhh1zOwWgc9a7OezKLzb1juozCADz4=; b=eB1T8Qw89fRn+H9z2V/3Bk5HdO6Vb2O5r2NopqdcSvY2VnIIBC89D9cnhiVffGOe2IxK nTKq0f6zme+rvIihxYPqz450453WRWm7BPbUsx9nHDKHAiXrOJD1rzqbIgbGf8l3BR0LX DypoB3uYg1Br60kpPivOxxrOiwsQXeMpynYTHwPG6ucTl2TKBfuWHmx3rookZm/pnn6nJ P0YOkwp38HdOmfJDmjkJyQP8iG5CD5ni230K73rxY1wivl54xoX4vBVLfpvK9ksklTeCJ bzx9zgXeW6p699aOkfk8SWMsbgdLXCgpjkmnr1DwX+ieIZdSpdePXGBc9tXvhNDLXBw== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b="Sh0TDG/G"; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3567D606A337; Sat, 7 Nov 2026 14:24:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=Sh0TDG/G Received: by smtp.kernel.org (Postfix) with ESMTPSA id D65251F0089F; Sat, 7 Nov 2026 14:24:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1794061451; bh=+ywgtp4ISDzmojhh1zOwWgc9a7OezKLzb1juozCADz4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Sh0TDG/GZMWfgB3qH/BVwsPfqtrC7Sx7AWTrL7+yaqx/Vk3q9PwssZA7ys9CYQZmd 77N9EulLH40qCPiLa+4YZzaEnje97B8e0ZM8ySgOQmJ7boIhvIoEq05ce+nkFoC3Hz 3ZDL/eqDaw2KwTw+4tDaMPrNfP/gKeUE8r4EMiTw= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Dibin Moolakadan Subrahmanian , Mitul Golani , Ankit Nautiyal , Joonas Lahtinen , Sasha Levin Subject: [PATCH 6.12 0556/1536] drm/i915/dmc: Add sanity check for DMC load address Date: Sat, 7 Nov 2026 08:42:52 -0500 Message-ID: <20261107135013.207706279@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261107134957.653319350@linuxfoundation.org> References: <20261107134957.653319350@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore X-Mailing-List: stable@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Dibin Moolakadan Subrahmanian [ Upstream commit 7dedc5bb11f95e96fe80757c924d8d9aa7327759 ] For DMC firmware header version 3, the firmware load address is stored in dmc_info->start_mmioaddr and later used by dmc_load_program(). Unlike the MMIO address table, the firmware load address is not validated. Add a sanity check to ensure it is within the valid range. BSpec: 69671, 68378 Fixes: 3d5928a168a9 ("drm/i915/xelpd: Pipe A DMC plugging") Cc: stable@vger.kernel.org Assisted-by: Claude-Code:Sonnet-5 Signed-off-by: Dibin Moolakadan Subrahmanian Reviewed-by: Mitul Golani Signed-off-by: Ankit Nautiyal Link: https://patch.msgid.link/20260922133535.3180973-6-dibin.moolakadan.subrahmanian@intel.com (cherry picked from commit 5e47ee5c76ca9becde8df4ad5202845b7ffcbc4c) Signed-off-by: Joonas Lahtinen [ sashal: Changed drm_err(display->drm, ...) to drm_err(&i915->drm, ...) because parse_dmc_fw_header() here has no display variable and uses i915. ] Signed-off-by: Sasha Levin --- drivers/gpu/drm/i915/display/intel_dmc.c | 55 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dmc_regs.h | 12 ++++ 2 files changed, 67 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 641dabf275e73..d99037132cef5 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -699,6 +699,55 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc, } } +/* + * Check if the load address is within the valid range for the given DMC ID. + */ +static bool dmc_load_addr_sanity_check(struct intel_dmc *dmc, + u32 start_addr, u32 payload_size, + int header_ver, enum intel_dmc_id dmc_id) +{ + u32 start_range, end_range, end_addr; + + if (header_ver != 3) + return true; + + switch (dmc_id) { + case DMC_FW_MAIN: + start_range = DMC_MAIN_PROGRAM_BASE_START; + end_range = DMC_MAIN_PROGRAM_BASE_END; + break; + case DMC_FW_PIPEA: + start_range = DMC_PIPEA_PROGRAM_BASE_START; + end_range = DMC_PIPEA_PROGRAM_BASE_END; + break; + case DMC_FW_PIPEB: + start_range = DMC_PIPEB_PROGRAM_BASE_START; + end_range = DMC_PIPEB_PROGRAM_BASE_END; + break; + case DMC_FW_PIPEC: + start_range = DMC_PIPEC_PROGRAM_BASE_START; + end_range = DMC_PIPEC_PROGRAM_BASE_END; + break; + case DMC_FW_PIPED: + start_range = DMC_PIPED_PROGRAM_BASE_START; + end_range = DMC_PIPED_PROGRAM_BASE_END; + break; + default: + MISSING_CASE(dmc_id); + return false; + } + + if (payload_size == 0) + end_addr = start_addr; + else if (check_add_overflow(start_addr, payload_size - 1, &end_addr)) + return false; + + if (start_addr < start_range || end_addr > end_range) + return false; + + return true; +} + static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, const u32 *mmioaddr, u32 mmio_count, int header_ver, enum intel_dmc_id dmc_id) @@ -842,6 +891,12 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, return 0; } + if (!dmc_load_addr_sanity_check(dmc, start_mmioaddr, payload_size, + dmc_header->header_ver, dmc_id)) { + drm_err(&i915->drm, "DMC %d: firmware has wrong load address\n", dmc_id); + return 0; + } + dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); if (!dmc_info->payload) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h index 1bf446f96a10c..cb788a318d8d8 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h @@ -87,6 +87,18 @@ #define TGL_PIPE_MMIO_END(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\ _TGL_PIPEB_MMIO_END) +/* For DMC header version v3*/ +#define DMC_MAIN_PROGRAM_BASE_START 0x80000 +#define DMC_MAIN_PROGRAM_BASE_END 0x86fff +#define DMC_PIPEA_PROGRAM_BASE_START 0x90000 +#define DMC_PIPEA_PROGRAM_BASE_END 0x96fff +#define DMC_PIPEB_PROGRAM_BASE_START 0x98000 +#define DMC_PIPEB_PROGRAM_BASE_END 0x9efff +#define DMC_PIPEC_PROGRAM_BASE_START 0x52000 +#define DMC_PIPEC_PROGRAM_BASE_END 0x53fff +#define DMC_PIPED_PROGRAM_BASE_START 0x59000 +#define DMC_PIPED_PROGRAM_BASE_END 0x5afff + #define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030) #define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C) #define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038) -- 2.53.0