From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794338213; b=hMT8qDvK4kFC9CCB4Vym4vZY82v4+krZieD5kPY+b8cRdFKBW94vIndP6ZwT+BQXFnOj 4mGhbAx37sEbNeidZIvC9XHT+s8l0CyNfjaIL0bdUJSQa7T6gxTtB3NkS8DUG0XtwSQeu h7yU23l7hYjtnRy6RNdgk/zLVD3r8/CcKHYWdqmy5EX9rBdWp9vSUspRks7NcYFFTy9/N FpXkIiDvXGcB6qeMxD9JTZpMcvFYhiOS/mKmrMK6TixWvAyY77MCwK+PrGcQqDb47+6ig vQStQBBbeIKxxMiwAF7PSlSbmXffYABZ5neds+XpRxlOQhZg3OLUVgFVjBu2z8veweA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794338213; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Transfer-Encoding; bh=o2POtgEWPTYJK24DPz1NX5FJSVdUXVqB0c1FKBqDgVM=; b=wEW0a1X8aUpZosDjt68D+WKjuBlE+zzKE7jKkaTzQ3xD6zBQQp89l7XpN9HNkXa7mGcZ KYLxuzUK/0uviSdrAaqnYfsRAIzG7skFXKP/LEv7PI8U0UjCfxJVzs+yJh837ik8D9bFT /kjav/xdHhUlLnlu+8NlM3taUFowhORcQc+SpXSuW5+VedIhQq4kBlTNAd1NUIiRdYLrT PXbdt62KqkXWx3uDFkjs0iWChvLG6B7vYHCFx+K4eZ0Llg2smTmEYAU1F2WfgEoZcBRBR x4tKrXdK0TcVaUi8n0U3tzTj7CRLfrGUGycFTWvJCXLbT6j1Qy3fpRcWc+VdSfOTc/w== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=XL36tSvG; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B832606A321 for ; Tue, 10 Nov 2026 19:16:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=XL36tSvG Received: by smtp.kernel.org (Postfix) with ESMTPSA id 12B741F0089F; Tue, 10 Nov 2026 19:16:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1794338213; bh=o2POtgEWPTYJK24DPz1NX5FJSVdUXVqB0c1FKBqDgVM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=XL36tSvGntAFij9lp/xIlQJX+SpdU7xNEJWY4pNkcwU1XbXvWOSYcgChVop+Lkp47 EH0+CfjrIK5bGKd5O80Ece+wUrIt+D+nXh6d3LXKgR5lf4vfkTMHsMO1b3BQEn09N3 XIzhx5r59phRQBYVNZbVSlZScRRX7W2n4NTpJwqnD+fZ0Bt3OGwK3fMjRTcWviHDZ1 IbYZK5g9zJYs18doj73oMQvBqAADBel1Mjer4GWafJhnNLswzLyzZsbyzy6tIikQPc rXbdXMX9S1SEmqVf/TTm8MnZSYdLVSYEviFyKmuhp/XnnWZYw+7yQcx/5wF+e73vZB jvdMuJpvXYsMg== From: Sasha Levin To: stable@vger.kernel.org Cc: Geraldo Nascimento , Dragan Simic , Shawn Lin , Manivannan Sadhasivam , Bjorn Helgaas , Sasha Levin Subject: [PATCH 6.6.y] PCI: rockchip: Drive at 2.5 GT/s, error other speeds Date: Tue, 10 Nov 2026 14:16:50 -0500 Message-ID: <20261110191340.3497523-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261107053432-failed-6.6-84d08ff902f1@kernel.org> References: <20261107053432-failed-6.6-84d08ff902f1@kernel.org> X-Mailing-List: stable@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Geraldo Nascimento [ Upstream commit 84d08ff902f1ec01177fef1a21a38934927f5aee ] Configure the core to be driven at 2.5 GT/s Link Speed and ignore any other speed with a warning. Also drop the 5.0 GT/s Link Speed defines from Rockchip PCIe header. The reason is that Shawn Lin from Rockchip has reiterated that there may be danger of "catastrophic failure" in using their PCIe with 5.0 GT/s speeds. While Rockchip has done so informally without issuing a proper errata, and the particulars are thus unknown, this may cause data loss or worse. This change is corroborated by RK3399 official datasheet [1], which states maximum link speed for this platform is 2.5 GT/s. [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver") Reported-by: Dragan Simic Reported-by: Shawn Lin Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/ Signed-off-by: Geraldo Nascimento Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Reviewed-by: Dragan Simic Reviewed-by: Shawn Lin Cc: stable@vger.kernel.org Link: https://patch.msgid.link/7421df7a7b7778ee99363cccfdfabbfa8aa6ab5e.1781622998.git.geraldogabriel@gmail.com [ sashal: adjusted patch context for the older Rockchip PCIe driver implementation ] Signed-off-by: Sasha Levin --- drivers/pci/controller/pcie-rockchip.c | 14 ++++++-------- drivers/pci/controller/pcie-rockchip.h | 3 --- 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index c07d7129f1c7c..6a970dc766d4d 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -66,8 +66,10 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) } rockchip->link_gen = of_pci_get_max_link_speed(node); - if (rockchip->link_gen < 0 || rockchip->link_gen > 2) - rockchip->link_gen = 2; + if (rockchip->link_gen < 0 || rockchip->link_gen >= 2) { + rockchip->link_gen = 1; + dev_warn(dev, "invalid max-link-speed, limited to 2.5 GT/s\n"); + } rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core"); if (IS_ERR(rockchip->core_rst)) { @@ -237,12 +239,8 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) goto err_exit_phy; } - if (rockchip->link_gen == 2) - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, - PCIE_CLIENT_CONFIG); - else - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, - PCIE_CLIENT_CONFIG); + rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, + PCIE_CLIENT_CONFIG); regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 049ad984a4164..4702caac56114 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -37,7 +37,6 @@ #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) -#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) #define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c) #define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002) #define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0) @@ -184,8 +183,6 @@ (((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2) #define PCIE_LINK_UP(x) \ (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP) -#define PCIE_LINK_IS_GEN2(x) \ - (((x) & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) #define RC_REGION_0_ADDR_TRANS_H 0x00000000 #define RC_REGION_0_ADDR_TRANS_L 0x00000000 -- 2.53.0