From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794338596; b=0PHmRfcAyy9LH27wJgALIps6H54Rzav18czYJlsXAdSwPqJ2LPGD6KZvGmWitJq0uFTe /sD3OJ9Le9uuEqpoL2CRAfP5bImFyC8MoD9ZcCciFRpFYCUtSIGt0dJYrdPVkpx5MqUFN f875j1IWS9TaFd3GKwj+J6qEqudq8e07m28Yvz4i+m7J7pl/8peQvkHNdA2o1X0dUc56E dYc7poXYwXkpRW4Fo0u5VY0ZNfNtuot6pHy+++H5375TbWUbOAAKXjy3WOAENZkM8ld+K R79C461GxN/mbVRkDeY/uOyfs9ajelOxm2izP3jqSBwf/loLHwkwiAaLehUUDu+0c0g== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794338596; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Transfer-Encoding; bh=BUX21rlUQrE7+iRB0Ubwz2n9WlMInWyZZAvHr23/uMQ=; b=2hdxzsiqXPHrYxYo51ljVrj2Vs+lX5bBK5SpjQLM/1dmSQAUn53zzOwh6m+9qRCJwrRV lGwmLlrdaekabkFC1ffQSXTNT2SeuvJYgsby3Wuod9+LyLYp4oNQrpujEFzkuAFDTeRYd JzbWVvnl24DOOIF/qVbZzYhwWTqDPAGv/GxqRztjxwEXmZDaV53/DzCtxKzgiVmA3LDR4 jpvNkhnWs0nDNXS58bWw4D3C3F5LCxnmapI46JpnbHXHqqXh7HwS9im1aqlJphoWYFaEk FbK6kXcEnDPc5/x5Xr7ggrmPnXG7iqa2AcwtwoPiOHHJWBSI4OX4Mxrn1068zQKMwTw== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=nwH2MkUF; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F6CA606A32D for ; Tue, 10 Nov 2026 19:23:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=nwH2MkUF Received: by smtp.kernel.org (Postfix) with ESMTPSA id DFBDA1F008A1; Tue, 10 Nov 2026 19:23:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1794338595; bh=BUX21rlUQrE7+iRB0Ubwz2n9WlMInWyZZAvHr23/uMQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=nwH2MkUFrQbhttU1fuY0U6L1CwGeSbUGHDaW5XdCg4+P9WaRD4etyAPYeIgbaulLP sIvzFtd+k+3LdCiAg1nTFLsZ3Jx35xCb9IoYYl8weQaDGJIyHLf1HlheocdhJ8v77z 9eLtS63AgN+9lgwDR5b0zdHZvaIuEXkE12g78bAsZCGAnfTwvgxg4AH89ZIvEsrpHh EPJMrbFUpDUg3vVlMoCV6dVHVhjRW/b3KboSOs6JaSjnJuK8KZzrTsvOLCXddHHrNN nmLUCdUJ6IRgPpjV7YnoQVW+GR+SpT6XT5FJ1F22LdDSSW3vNoPECGrJOYM35ngwKb HBbJi30IVDobQ== From: Sasha Levin To: stable@vger.kernel.org Cc: Geraldo Nascimento , Dragan Simic , Shawn Lin , Manivannan Sadhasivam , Bjorn Helgaas , Sasha Levin Subject: [PATCH 6.1.y] PCI: rockchip: Drive at 2.5 GT/s, error other speeds Date: Tue, 10 Nov 2026 14:23:13 -0500 Message-ID: <20261110192249.3537377-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261107054811-failed-6.1-84d08ff902f1@kernel.org> References: <20261107054811-failed-6.1-84d08ff902f1@kernel.org> X-Mailing-List: stable@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Geraldo Nascimento [ Upstream commit 84d08ff902f1ec01177fef1a21a38934927f5aee ] Configure the core to be driven at 2.5 GT/s Link Speed and ignore any other speed with a warning. Also drop the 5.0 GT/s Link Speed defines from Rockchip PCIe header. The reason is that Shawn Lin from Rockchip has reiterated that there may be danger of "catastrophic failure" in using their PCIe with 5.0 GT/s speeds. While Rockchip has done so informally without issuing a proper errata, and the particulars are thus unknown, this may cause data loss or worse. This change is corroborated by RK3399 official datasheet [1], which states maximum link speed for this platform is 2.5 GT/s. [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver") Reported-by: Dragan Simic Reported-by: Shawn Lin Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/ Signed-off-by: Geraldo Nascimento Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Reviewed-by: Dragan Simic Reviewed-by: Shawn Lin Cc: stable@vger.kernel.org Link: https://patch.msgid.link/7421df7a7b7778ee99363cccfdfabbfa8aa6ab5e.1781622998.git.geraldogabriel@gmail.com [ sashal: adjusted context to match the existing Rockchip PCIe initialization code and HIWORD_UPDATE register macros ] Signed-off-by: Sasha Levin --- drivers/pci/controller/pcie-rockchip.c | 14 ++++++-------- drivers/pci/controller/pcie-rockchip.h | 3 --- 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index bdce1ba7c1bc0..c1567a2ef1890 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -65,8 +65,10 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) } rockchip->link_gen = of_pci_get_max_link_speed(node); - if (rockchip->link_gen < 0 || rockchip->link_gen > 2) - rockchip->link_gen = 2; + if (rockchip->link_gen < 0 || rockchip->link_gen >= 2) { + rockchip->link_gen = 1; + dev_warn(dev, "invalid max-link-speed, limited to 2.5 GT/s\n"); + } rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core"); if (IS_ERR(rockchip->core_rst)) { @@ -236,12 +238,8 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) goto err_exit_phy; } - if (rockchip->link_gen == 2) - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, - PCIE_CLIENT_CONFIG); - else - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, - PCIE_CLIENT_CONFIG); + rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, + PCIE_CLIENT_CONFIG); regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 049ad984a4164..4702caac56114 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -37,7 +37,6 @@ #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) -#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) #define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c) #define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002) #define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0) @@ -184,8 +183,6 @@ (((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2) #define PCIE_LINK_UP(x) \ (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP) -#define PCIE_LINK_IS_GEN2(x) \ - (((x) & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) #define RC_REGION_0_ADDR_TRANS_H 0x00000000 #define RC_REGION_0_ADDR_TRANS_L 0x00000000 -- 2.53.0