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From: Sasha Levin <sashal@kernel.org>
To: stable@vger.kernel.org
Cc: Elena Sakhnovitch <Elena.Sakhnovitch@amd.com>,
	Shahzeb Ahmed <shahzeb.ahmed@amd.com>,
	Manjunath Gaonkar <Manjunath.Gaonkar@amd.com>,
	Apurv Mishra <apurv.mishra@amd.com>,
	Alex Deucher <alexander.deucher@amd.com>,
	Sasha Levin <sashal@kernel.org>
Subject: [PATCH 6.12.y 4/4] drm/amdgpu/gmc9: add extra type-2 TLB flush for gfx942/gfx950
Date: Tue, 10 Nov 2026 15:09:55 -0500	[thread overview]
Message-ID: <20261110200933.3702189-4-sashal@kernel.org> (raw)
In-Reply-To: <20261110200933.3702189-1-sashal@kernel.org>

From: Elena Sakhnovitch <Elena.Sakhnovitch@amd.com>

[ Upstream commit 232213c9bd7f703836164f23160b76657094a7db ]

Add extra type-2 TLB flush for GC 9.5.0, similar race condition was
observed as Vega20+XGMI. Add to GC 9.4.3 and 9.4.4 too, as they share
the same multi-XCD TLB topology.

Reported-by: Shahzeb Ahmed <shahzeb.ahmed@amd.com>
Reported-by: Manjunath Gaonkar <Manjunath.Gaonkar@amd.com>
Signed-off-by: Elena Sakhnovitch <Elena.Sakhnovitch@amd.com>
Reviewed-by: Apurv Mishra <apurv.mishra@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 138cfb165ae6aa98c0767b431e718d1a8199db28)
Cc: stable@vger.kernel.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index c095a1489bd80..06e4b393d1ce6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -2324,10 +2324,22 @@ static int gmc_v9_0_hw_init(void *handle)
 	 * (type 2), which flushes both. Due to a race condition with
 	 * concurrent memory accesses using the same TLB cache line, we still
 	 * need a second TLB flush after this.
+	 *
+	 * GC 9.4.3, 9.4.4 and 9.5.0 hit a similar race.
 	 */
-	adev->gmc.flush_tlb_needs_extra_type_2 =
-		amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) &&
-		adev->gmc.xgmi.num_physical_nodes;
+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
+	case IP_VERSION(9, 4, 0):
+		adev->gmc.flush_tlb_needs_extra_type_2 =
+			adev->gmc.xgmi.num_physical_nodes;
+		break;
+	case IP_VERSION(9, 4, 3):
+	case IP_VERSION(9, 4, 4):
+	case IP_VERSION(9, 5, 0):
+		adev->gmc.flush_tlb_needs_extra_type_2 = true;
+		break;
+	default:
+		break;
+	}
 
 	/* The sequence of these two function calls matters.*/
 	gmc_v9_0_init_golden_registers(adev);
-- 
2.53.0


      parent reply	other threads:[~2026-11-10 20:10 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-07 10:24 FAILED: patch "[PATCH] drm/amdgpu/gmc9: add extra type-2 TLB flush for gfx942/gfx950" failed to apply to 6.12-stable tree Sasha Levin
2026-11-10 20:09 ` [PATCH 6.12.y 1/4] drm/amd: define gc ip version local variable Sasha Levin
2026-11-10 20:09   ` [PATCH 6.12.y 2/4] drm/amd: update mtype flags for gfx 9.5.0 Sasha Levin
2026-11-10 20:09   ` [PATCH 6.12.y 3/4] drm/amdkfd: Drop workaround for GC v9.4.3 revID 0 Sasha Levin
2026-11-10 20:09   ` Sasha Levin [this message]

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