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Tue, 10 Nov 2026 19:44:23 -0600 From: Wayne Lin To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Wenjing Liu , Dillon Varone , Mario Limonciello , "Alex Deucher" , , Wayne Lin Subject: [PATCH 61/74] drm/amd/display: Read DRAM channel width from SMU init table Date: Wed, 11 Nov 2026 09:29:07 +0800 Message-ID: <20261111014100.3596072-62-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261111014100.3596072-1-Wayne.Lin@amd.com> References: <20261111014100.3596072-1-Wayne.Lin@amd.com> X-Mailing-List: stable@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: EA8PEPF0000000B:EE_|MN0PR12MB5860:EE_ X-MS-Office365-Filtering-Correlation-Id: a2985b7d-7d60-46c0-1b88-08df3f955610 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|1800799024|82310400026|36860700016|261009223027099003|261021123027099003|261021121427099003|10067099003|261022113327099003|261102123227099003|260925021311599003|260925021911599003|260925022911599003|11063799006|56012099006|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nSwvXOJNtRsB8g/g09hFGnvjCu8VucRukg0AzsjvcTFcN9XFNbrFUjGbmLYq5ozqwEMhWqkcT6QXrN4BwUvcnEnC3173JSgWd/wFeeWf+iX0818h6BSqEy3wDT8ZzlH/lJgPY0/rhtK/8jKyBaOlazAU6+Zh0p4M5UMhvA0Uo9WQXakSp13IjWLSBTXriWaUhxBT7Rm4gXw4kzZXhWV9oeme5aAkPXd4j57wZF7ydAZOSYD9rvAa3rOn3tQnIO5vFN5NUl2WDZvwmgA20C1qMyugeSuiPQ74hDtfn8uXflr9G3pzDvRM9kAyWfKAib4G44OTGFhbTpNAejWvTXop/YS+gE6+XUSR38SC0Mh5PZkhFE2LfzBHF6gcaltTM9SheVRMUh90FRq5nAt1yYSjIIBdX+IdHwlT2quXzcuAKByys1nIfobMmEUcvl5vxJSK X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2026 01:44:33.5109 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2985b7d-7d60-46c0-1b88-08df3f955610 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: EA8PEPF0000000B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5860 From: Wenjing Liu [Why] The channel count came from the SMU init table but the channel width came from VBIOS vram info. Both values need to describe the same memory type. [How] Add DramChannelWidthBytes to MemoryConfig_t, using a reserved slot so the layout is unchanged. Populate the channel width in bw_params from the init table instead of VBIOS vram info. Cc: Dillon Varone Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Wenjing Liu Signed-off-by: Wayne Lin --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h | 3 ++- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 3 +-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h index 234777bdd183..ea3927223117 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h @@ -77,7 +77,8 @@ typedef struct { typedef struct { uint32_t NumUmcChannels; - uint32_t Reserved[3]; + uint32_t DramChannelWidthBytes; + uint32_t Reserved[2]; } MemoryConfig_t; /** diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c index 8eee54c7d5d5..c5d56757eafd 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c @@ -747,8 +747,7 @@ static bool dcn60_fetch_dal_init_table(struct clk_mgr_internal *clk_mgr) //dcn60_populate_dc_mode_limit(&bw_params->dc_mode_limit, init_table); bw_params->num_channels = init_table->MemoryConfig.NumUmcChannels; - bw_params->dram_channel_width_bytes = - clk_mgr->base.ctx->dc_bios->vram_info.dram_channel_width_bytes; + bw_params->dram_channel_width_bytes = init_table->MemoryConfig.DramChannelWidthBytes; dcn60_populate_utm_qos_model(clk_mgr, &bw_params->utm_qos_model, init_table); -- 2.43.0