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Tue, 10 Nov 2026 19:45:12 -0600 From: Wayne Lin To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Jing Zhou , Nicholas Kazlauskas , Charlene Liu , "Mario Limonciello" , Alex Deucher , , Wayne Lin Subject: [PATCH 68/74] drm/amd/display: Seed boot clocks to avoid lowering pre-OS display clocks Date: Wed, 11 Nov 2026 09:29:14 +0800 Message-ID: <20261111014100.3596072-69-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261111014100.3596072-1-Wayne.Lin@amd.com> References: <20261111014100.3596072-1-Wayne.Lin@amd.com> X-Mailing-List: stable@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000204:EE_|CH3PR12MB7738:EE_ X-MS-Office365-Filtering-Correlation-Id: 07b4db1e-8c1e-40c1-6b64-08df3f957367 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|1800799024|82310400026|36860700016|10067099003|11063799006|56012099006|261022105027099003|261022075727099003|261021123027099003|261021121427099003|261026121527099003|261026140227099003|261021135927099003|261028144727099003|261102123227099003|261009223027099003|22082099003|18002099003|6133799003; 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Its link detection runs prepare_phy_clocks(), which goes through clk_mgr_exit_optimized_pwr_state() and clk_mgr_optimize_pwr_state() and calls update_clocks(dc->current_state). At that point both dc->current_state->bw_ctx.bw.dcn.clk and clk_mgr->clks are still zero, because init_clocks() memsets them. On the safe_to_lower path, dcn42_update_clocks() clamps the requested DPPCLK to the 100MHz floor and programs it. This drops DPPCLK below what the GOP-lit eDP pipe needs, and the panel flashes white. [HOW] 1. In dcn42_init_clocks() and dcn42b_init_clocks(), seed clk_mgr->clks dispclk/dppclk from the boot snapshot(10kHz units, x10). 2. Add a DC core helper, sync_current_state_clocks_from_clk_mgr(). After every hwss.init_hw() call (legacy_hardware_init, D0 entry in dc_set_power_state, and dc_reinitialize_hardware), it copies clk_mgr->clks into dc->current_state->bw_ctx.bw.dcn.clk for DCN. A later update_clocks() before the first commit then sees the real pre-OS clocks and does not lower them. Raising clocks is still allowed and does not cause a flash. Cc: Nicholas Kazlauskas Cc: Charlene Liu Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Jing Zhou Signed-off-by: Wayne Lin --- .../amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 3 +++ .../display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c | 4 ++++ drivers/gpu/drm/amd/display/dc/core/dc.c | 16 +++++++++++++++- 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index b1fbadd0d885..054eab1e0cb9 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -643,6 +643,9 @@ DC_LOGGER_INIT(clk_mgr_base->ctx->logger); DC_LOG_SMU("dp_dto_source_clock %d, dprefclk %d\n", clk_mgr_base->dp_dto_source_clock_in_khz, clk_mgr_base->dprefclk_khz); dcn42_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr); + /* Snapshot is in 10kHz units; seed clks so update_clocks() does not lower the pre-OS clocks */ + clk_mgr_base->clks.dispclk_khz = clk_mgr_base->boot_snapshot.dispclk * 10; + clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk * 10; clk_mgr_base->clks.ref_dtbclk_khz = clk_mgr_base->boot_snapshot.dtbclk * 10; clk_mgr_base->clks.dtbclk_en = clk_mgr_base->boot_snapshot.dtbclk > 59000; } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c index 57291c10c917..5e8a65f1ee68 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c @@ -251,6 +251,10 @@ DC_LOGGER_INIT(clk_mgr_base->ctx->logger); DC_LOG_SMU("dp_dto_source_clock %d, dprefclk %d\n", clk_mgr_base->dp_dto_source_clock_in_khz, clk_mgr_base->dprefclk_khz); dcn42b_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr); + + /* Snapshot is in 10kHz units; seed clks so update_clocks() does not lower the pre-OS clocks */ + clk_mgr_base->clks.dispclk_khz = clk_mgr_base->boot_snapshot.dispclk * 10; + clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk * 10; } static struct clk_bw_params dcn42b_bw_params = { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8a02bcbb9649..463a3fc2d8c2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1728,12 +1728,25 @@ static void detect_edp_presence(struct dc *dc) } } +static void sync_current_state_clocks_from_clk_mgr(struct dc *dc) +{ + if (!dc->current_state || !dc->clk_mgr) + return; + + if (!(dc->ctx->dce_version == DCN_VERSION_4_2 || dc->ctx->dce_version == DCN_VERSION_4_2B)) + return; + + dc->current_state->bw_ctx.bw.dcn.clk = dc->clk_mgr->clks; +} + void legacy_hardware_init(struct dc *dc) { detect_edp_presence(dc); - if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW) + if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW) { dc->hwss.init_hw(dc); + sync_current_state_clocks_from_clk_mgr(dc); + } dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); } @@ -6435,6 +6448,7 @@ void dc_set_power_state(struct dc *dc, enum dc_acpi_cm_power_state power_state) dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state); dc->hwss.init_hw(dc); + sync_current_state_clocks_from_clk_mgr(dc); invalidate_drr_adjust(dc); -- 2.43.0