From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794363968; b=UYimV5ltRQKyhzWoPbCem+gZ6SkYllibCQO5q6z5wMJgpu6Duw+EFVLNrBWAWQunf+zX ny3u/AV/fPIQo+6Z4jtCns9U/+utxgu/EdEgHFKoyeXEmQkJF6Ykgon6ocNk+yJANqqyc UyVpA6KNApSPFcBNhhtzqaSA8s2w3Nvtsb6VPGVPfMCRKijO/+vvdN9pXXEUDs3aRQvfj RERe8hEt6nILOxIlZqs05NIbkD0fFwlWbzxLUdrYTb8yaXMlqWWd2em60IWeKOWUv9hxS wjuPdo+Ubxi6Vuyfgw7lan3jiQGwnW6ar4HGpI+JBAMIbTc9/yR7XYyurSIwltAMotg== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794363968; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Transfer-Encoding; bh=fXQgqRS5RuHlwejzP3gzn3DI2JuTuzqG5csyN9fwq5k=; b=msLmVvrKtbT55yRn60TSrjzG0CV98QX09DyynYTqKkgEZm5lCQnW+2dedOy7DuYqz71E LWC5L3wTmXX86qlqOKPaTnx8Bf92/jtzDIUxdHATNJlvEzgyXnPSKscVIgJXLYk+/nNA8 6J8il69P5hnAqrsbjvkJC0lppBFZ7VBYndeJnEZBKHEYb/JBrMg15LiDcl+A2yj5KvjsK LO0VRzFzkI5AZnrW6kwWzbMUxgf7LBmGk5cFE/WDPQUxaNMxmY70V8cblNzrt9ND8AIzy tD8w7B0QOQjiQVNsksDDmhyhdTsX1c1truMYePzPcYEQKCHjWhzJjkhOM+17nSeqyBA== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=KepES96W; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34D04606A326 for ; Wed, 11 Nov 2026 02:26:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=KepES96W Received: by smtp.kernel.org (Postfix) with ESMTPSA id 90AF71F0089F; Wed, 11 Nov 2026 02:26:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1794363968; bh=fXQgqRS5RuHlwejzP3gzn3DI2JuTuzqG5csyN9fwq5k=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KepES96WBELRI7ffm6wOLiBO5GPeMiCUtvOpRftBjHxQOqD9O4ZPnzypHzwPmRpcs YqQdAzI329OjSxMzI60VfadUpt3YyYR2N2tdIL4sG8LpYlMqAVPh4ImgTAOxSB2A5y 0rKx4iJCDakQKZHN6atIREsmU40y/sPN1ngZ76DmHXlL475ubA/rRfnAVM8H7KVZCZ 28MX69NoGBlpxHt1sseOj2XdjEXHxzqOpwqvLRd9O3xT6MUd4CDL0zOPM7os4bsBmK S7TndLTRTWrDxAXUfwrcZ4FQCReV1EpH66bJCZuFbKIiF/bqQCIw4uIwLjKUSR4uLP MmPm80fVSieHA== From: Sasha Levin To: stable@vger.kernel.org Cc: Maciej Kucharek , Alex Deucher , Sasha Levin Subject: [PATCH 6.1.y] drm/amdgpu: reset SI ASIC on MacBookPros with VRAM at 0 Date: Tue, 10 Nov 2026 21:26:06 -0500 Message-ID: <20261111022542.613290-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261107055213-failed-6.1-5b56ede88031@kernel.org> References: <20261107055213-failed-6.1-5b56ede88031@kernel.org> X-Mailing-List: stable@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Maciej Kucharek [ Upstream commit 5b56ede880317bd912f914d5cd38ba1d357677fa ] On MacBookPros with switchable graphics, the firmware puts VRAM at MC address 0 when the iGPU is enabled. The EFI stub enables the iGPU on these machines through apple_set_os(). On a MacBookPro11,5 (Radeon R9 M370X, 1002:6821, subsystem 106b:0149), the driver adopts this layout at init: MC_VM_FB_LOCATION=0x007f0000, HDP_NONSURFACE_BASE=0 VRAM at 0x0-0x7fffffff, GART table at 0x1400000 The driver posts the ASIC again on S3 resume and after a GPU reset. The VBIOS asic_init table then moves VRAM back to the VBIOS default: MC_VM_FB_LOCATION=0xf47ff400, HDP_NONSURFACE_BASE=0xf4000000 gmc_v6_0 does not reprogram these registers. The GART table is then no longer in VRAM, and the gfx ring test times out: amdgpu: ring gfx test failed (-110) amdgpu: resume of IP block failed -110 Reset and post the ASIC at driver load on Apple boards with VRAM at 0. The driver then uses the VBIOS layout (VRAM at 0xf400000000) from the start, and later posts keep it. After the reset, FB_BASE is not 0, so a module reload does not reset the ASIC again. The test is the same one that commit c54e4d105077 ("drm/amdgpu: make Mac FB workaround generic") uses: an Apple subsystem vendor and VRAM at 0. The VI quirk for the MacBookPro14,3 resets at load for the same reason: commit b6b1d9721851 ("drm/amdgpu: reset VI ASIC on MacBookPro14,3") Other Apple SI boards get the same reset if FB_BASE reads 0 at load. Tested on a MacBookPro11,5 with 7.2.5 and this patch: the panel comes up at boot, and 4 of 4 deep S3 cycles resume. Without the patch, S3 resume fails every time. The GPU reset path is not tested. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/5978 Assisted-by: Claude:claude-opus-5-5 Reviewed-by: Alex Deucher Signed-off-by: Maciej Kucharek Signed-off-by: Alex Deucher (cherry picked from commit 60dd16ae10f286cb9cce5b6027b2d5ee869637af) Cc: stable@vger.kernel.org [ sashal: Replaced the unavailable MC_VM_FB_LOCATION__FB_BASE_MASK macro with its equivalent literal 0xFFFF. ] Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/si.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index fd34c2100bd96..c63f1b7162d34 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1509,6 +1509,16 @@ static bool si_need_full_reset(struct amdgpu_device *adev) static bool si_need_reset_on_init(struct amdgpu_device *adev) { + /* + * MacBookPros with switchable graphics put VRAM at 0 when the iGPU + * is enabled. Any later post (S3 resume, GPU reset) moves it back to + * the vbios default, so reset and post on load to start with the + * vbios layout. + */ + if (adev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && + !(RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF)) + return true; + return false; } -- 2.53.0