From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794585895; b=gnNAj14RXJUDM0gX5Z2lc5slbvAHQylJbUJGH5t0nO8QMZ8TYrcvtnwnpGdWZnkbiL5+ 6nchonHSpAUbMbDJfbLiO5yDiFYYxe9IlydDX23LgaYQEmvdmhrpoIP9vxdA8rGI9NID2 he5cRvt3o+j/6kd6TiuiBqzT6j84X5RPGhCxI9kTk7MKoa9VTDjduwvpytDNBgrW3WzXX TCM9RvenzPPM7MEJQO36wQb/pnhW9BWmSRbCQDpPgcgttqNySvGMkpcREac0OSd4nfTSz V+lmauzA6SNLbNogFrvsZxVqPRlaYv2Y5RR5y25stKxugIE02T0SK+PYoUgnczgErpg== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794585895; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:User-Agent:X-stable:X-Patchwork-Hint: MIME-Version:Content-Transfer-Encoding; bh=1UtH+0f3gdx9Y+eh7htv2YcnicwUVglubUm+qlfyxGI=; b=aAHOjxiR2fgh2GYs/OBHSamW5V5st7dKTz79GHQUxtMygK3WAHpOYoQSXLU1+6H5NUgU WFMtW8lwplyO3H6oI6EGzT/ETGiNMHNIkryk14x4utFrnLBQySSowskxF6gA4qD/6mOi0 LgU2HZQCRWwLkbEOp6thMOrzpwH6Kq0djTznu/TF/R4QQ05THeCqvsNCm6BI3L3Q6iO8C d9cRhU0jVW9vOE7vS3BcEsXXXAwYO6gyuzk4eosWvm3wEAJyk6KTzvqIQGKbgNxsRwBm7 sfSl1dJQ5eFQOcaDiKmpHwUM036foXPb+ixcy15GTk6WyJtPJdtuRF1SuiG+9JPQZ3w== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=cAt5g1ay; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E70BE606EA94; Fri, 13 Nov 2026 16:04:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=cAt5g1ay Received: by smtp.kernel.org (Postfix) with ESMTPSA id 957D51F000C4; Fri, 13 Nov 2026 16:04:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1794585894; bh=1UtH+0f3gdx9Y+eh7htv2YcnicwUVglubUm+qlfyxGI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=cAt5g1ayQR50LCaQ9emBa0GKDiv74uKP8Ilz9qk34DA9bxirsrvEugpNp1SKaTJ/D mbKdWqRBUEzWZ+C18x8CRBqMn3Xm0fIxyTOfectgXdgfVp4fqoe7pZZpFAnhHiAR7b ry3Q9pwfbXlvlfjD2MxA8dQ3FQs9HLCyFOyJ9FRM= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Imre Kaloz , Thomas Bogendoerfer , Sasha Levin Subject: [PATCH 7.3 418/507] MIPS: sgi-ip32: Leave MACE PCI control alone in config accesses Date: Fri, 13 Nov 2026 10:52:02 -0500 Message-ID: <20261113153810.898783550@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261113153753.358973689@linuxfoundation.org> References: <20261113153753.358973689@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore X-Mailing-List: stable@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 7.3-stable review patch. If anyone has any objections, please let me know. ------------------ From: Imre Kaloz [ Upstream commit a55a7df2cf788234850d9053ecc25a5470175929 ] mace_pci_read_config() clears the master abort interrupt enable in the MACE PCI control register around each config read. A register read followed by two register writes can hang CRIME 1.1 under DMA load. Ack master aborts in the error register instead, and follow every write with a read so back-to-back accesses cannot form that sequence. Fixes: c990081bf87b ("[MIPS] Fix IP32 breakage") Cc: stable@vger.kernel.org Signed-off-by: Imre Kaloz Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/pci/ops-mace.c | 26 +++++++++++++++++++------- arch/mips/pci/pci-ip32.c | 2 ++ 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c index 951d8070fb486..8827e5f2ea460 100644 --- a/arch/mips/pci/ops-mace.c +++ b/arch/mips/pci/ops-mace.c @@ -35,15 +35,27 @@ static inline int mkaddr(struct pci_bus *bus, unsigned int devfn, (reg & 0xfc); } +/* + * On CRIME 1.1, a MACE PCI register read followed by two register writes + * can hang the machine under DMA load, so every register write in this + * file is followed by a read. Config cycles to empty slots end in a + * master abort; ack it with interrupts still off so the bridge error + * interrupt does not report it. + */ +static void mace_pci_ack_abort(void) +{ + u32 error = mace->pci.error; + + if (error & MACEPCI_ERROR_MASTER_ABORT) { + mace->pci.error = error & ~MACEPCI_ERROR_MASTER_ABORT; + mace->pci.error; + } +} static int mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 *val) { - u32 control = mace->pci.control; - - /* disable master aborts interrupts during config read */ - mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT; mace->pci.config_addr = mkaddr(bus, devfn, reg); switch (size) { case 1: @@ -56,9 +68,7 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, *val = mace->pci.config_data.l; break; } - /* ack possible master abort */ - mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT; - mace->pci.control = control; + mace_pci_ack_abort(); /* * someone forgot to set the ultra bit for the onboard * scsi chips; we fake it here @@ -77,6 +87,7 @@ mace_pci_write_config(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 val) { mace->pci.config_addr = mkaddr(bus, devfn, reg); + mace->pci.error; switch (size) { case 1: mace->pci.config_data.b[(reg & 3) ^ 3] = val; @@ -88,6 +99,7 @@ mace_pci_write_config(struct pci_bus *bus, unsigned int devfn, mace->pci.config_data.l = val; break; } + mace_pci_ack_abort(); DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val); diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c index 30aca6f76563d..41ec8453c865d 100644 --- a/arch/mips/pci/pci-ip32.c +++ b/arch/mips/pci/pci-ip32.c @@ -77,6 +77,8 @@ static irqreturn_t macepci_error(int irq, void *dev) } mace->pci.error = flags; + /* follow the write with a read, see mace_pci_ack_abort() */ + mace->pci.error; return IRQ_HANDLED; } -- 2.53.0