From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp91.ord1c.emailsrvr.com ([108.166.43.91]:55337 "EHLO smtp91.ord1c.emailsrvr.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751108AbeADXjc (ORCPT ); Thu, 4 Jan 2018 18:39:32 -0500 Received: from smtp20.relay.ord1c.emailsrvr.com (localhost [127.0.0.1]) by smtp20.relay.ord1c.emailsrvr.com (SMTP Server) with ESMTP id 4A79EE022E for ; Thu, 4 Jan 2018 18:39:32 -0500 (EST) Received: from smtp91.ord1d.emailsrvr.com (relay.ord1c.rsapps.net [172.28.255.120]) by smtp20.relay.ord1c.emailsrvr.com (SMTP Server) with ESMTPS id 4628FE01D3 for ; Thu, 4 Jan 2018 18:39:32 -0500 (EST) From: Kenneth Graunke To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. Date: Thu, 04 Jan 2018 15:39:23 -0800 Message-ID: <2209082.bMokASrcsY@kirito> In-Reply-To: <151510098613.6838.1512668093211672119@mail.alporthouse.com> References: <20180104193805.3872-1-kenneth@whitecape.org> <151510098613.6838.1512668093211672119@mail.alporthouse.com> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart6801100.tMfGarOYR5"; micalg="pgp-sha256"; protocol="application/pgp-signature" Sender: stable-owner@vger.kernel.org List-ID: --nextPart6801100.tMfGarOYR5 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote: > Quoting Kenneth Graunke (2018-01-04 19:38:05) > > Geminilake requires the 3D driver to select whether barriers are > > intended for compute shaders, or tessellation control shaders, by > > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when > > switching pipelines. Failure to do this properly can result in GPU > > hangs. > > > > Unfortunately, this means it needs to switch mid-batch, so only > > userspace can properly set it. To facilitate this, the kernel needs > > to whitelist the register. > > > > Signed-off-by: Kenneth Graunke > > Cc: stable@vger.kernel.org > > --- > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ > > 2 files changed, 7 insertions(+) > > > > Hello, > > > > We unfortunately need to whitelist an extra register for GPU hang fix > > on Geminilake. Here's the corresponding Mesa patch: > > Thankfully it appears to be context saved. Has a w/a name been assigned > for this? > -Chris There doesn't appear to be one. The workaround page lists it, but there is no name. The register description has a note saying that you need to set this, but doesn't call it out as a workaround. That's why I put a generic comment, rather than the name. --Ken --nextPart6801100.tMfGarOYR5 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. Content-Transfer-Encoding: 7Bit -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE6OtbNAgc4e6ibv4ZW1vaBx1JzDgFAlpOuysACgkQW1vaBx1J zDjQMw/9FVaoYwcbxpKH/xsJ1vYtdKa3BB3wDlmlNjOgBV9NfrOLhjq4UHvjOitK eGOng9i+M38qVKL4PMG9b/cyuMNKdCPIIPA2Z686bmhj3P9gFgVMSkITNcre4Ab3 dAbOZZ6kcj66KLf58IHKry5LJUHf7Lz5h6ApQRuqfazbifv1ChKNP1/w7bOHIuTn Wri4dhZasjmGRYHG12q9K7UZ8Zzr6jBw++ljbGGGKOAz9rDlO5LAJY3UdxiySYU1 ZdyAUxYg+W34B18EWZWIyzWCedNha1Nzkhk+PMpz/+P8M8+c8Gza6+JTwYiMvxb/ mDFqEd53rPqgpsXQ4AtGNjRqSDFuzS4uWZkGRXZveIEIrgj/4T/ZdNB7ZKvmO7/N 2hwRBH0YO92A4eeNmnC4dt+p7bUGqRUA/TgzWXNqM/2OMW2bbGyao6/tqN/T8Mm9 Z+dL9GLh0A/5iCwlY17sQRuMYVCynQpq50bECYXs2xO4GzCy545IVrsOGYzWcfDd 8jxz8qZ0zOhaEauxKvqascUTohBpJo8O4S0qtivWFKtzBTHmMHhGbRcw9dJXlPyl Av7cpa7BgFofo4bEGZ2OCZpbcPpnLUF0EKp1PFUTHqbxPqFCVMkGuapRurvcaF7U y3u5Qq71RiIygwxSpoAN/6t741mKMF1b8duhfa1LNSWyBeUUhbQ= =bxTk -----END PGP SIGNATURE----- --nextPart6801100.tMfGarOYR5--