PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up

PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up

[Marek Vasut]

Please backport the following commit into Linux v5.4 and newer stable 
releases:

80dc18a0cba8dea42614f021b20a04354b213d86

The backport will likely depend on macro rename commit:

817f989700fddefa56e5e443e7d138018ca6709d

This part of commit description clarifies why this is a fix:

"
As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds
greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link
training completes before sending a Configuration Request.
"

In practice, this makes detection of PCIe Gen3 and Gen4 SSDs reliable on
Renesas R-Car V4H SoC. Without this commit, the SSDs sporadically do not
get detected, or sometimes they link up in Gen1 mode.

This fixes commit

886bc5ceb5cc ("PCI: designware: Add generic dw_pcie_wait_for_link()")

which is in v4.5-rc1-4-g886bc5ceb5cc3 , so I think this fix should be 
backported to all currently maintained stable releases, i.e. v5.4+ .

Thank you

-- 
Best regards,
Marek Vasut

Re: PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up

[Greg KH]

On Wed, Aug 20, 2025 at 12:39:05AM +0200, Marek Vasut wrote:
> Please backport the following commit into Linux v5.4 and newer stable
> releases:
> 
> 80dc18a0cba8dea42614f021b20a04354b213d86
> 
> The backport will likely depend on macro rename commit:
> 
> 817f989700fddefa56e5e443e7d138018ca6709d
> 
> This part of commit description clarifies why this is a fix:
> 
> "
> As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds
> greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link
> training completes before sending a Configuration Request.
> "
> 
> In practice, this makes detection of PCIe Gen3 and Gen4 SSDs reliable on
> Renesas R-Car V4H SoC. Without this commit, the SSDs sporadically do not
> get detected, or sometimes they link up in Gen1 mode.
> 
> This fixes commit
> 
> 886bc5ceb5cc ("PCI: designware: Add generic dw_pcie_wait_for_link()")
> 
> which is in v4.5-rc1-4-g886bc5ceb5cc3 , so I think this fix should be
> backported to all currently maintained stable releases, i.e. v5.4+ .

Can you send backported and tested patches for these kernels so that we
know they work properly?

thanks,

gre gk-h

Re: PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up

[Marek Vasut]

On 8/25/25 9:39 AM, Greg KH wrote:
> On Wed, Aug 20, 2025 at 12:39:05AM +0200, Marek Vasut wrote:
>> Please backport the following commit into Linux v5.4 and newer stable
>> releases:
>>
>> 80dc18a0cba8dea42614f021b20a04354b213d86
>>
>> The backport will likely depend on macro rename commit:
>>
>> 817f989700fddefa56e5e443e7d138018ca6709d
>>
>> This part of commit description clarifies why this is a fix:
>>
>> "
>> As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds
>> greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link
>> training completes before sending a Configuration Request.
>> "
>>
>> In practice, this makes detection of PCIe Gen3 and Gen4 SSDs reliable on
>> Renesas R-Car V4H SoC. Without this commit, the SSDs sporadically do not
>> get detected, or sometimes they link up in Gen1 mode.
>>
>> This fixes commit
>>
>> 886bc5ceb5cc ("PCI: designware: Add generic dw_pcie_wait_for_link()")
>>
>> which is in v4.5-rc1-4-g886bc5ceb5cc3 , so I think this fix should be
>> backported to all currently maintained stable releases, i.e. v5.4+ .
> 
> Can you send backported and tested patches for these kernels so that we
> know they work properly?
Since the affected device I have available locally and the controller 
driver are only in Linux 6.12.y , I sent the two backports to stable@ 
for 6.12.y only . I hope they are OK .