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AJvYcCXZuOXAU9GJCQTcEoupulLp12FYa5LM3PC91ZQ3oM7FpPcaEpyn08pJJ+nP1Ss8KRkzBMSALSOUJZW3GUyS2BZQxGK4Y+sK X-Gm-Message-State: AOJu0Yy6mfNJnOoN/kSwNNcapKF5+oW4tjKSkF0dPHSgh2nuwm8OGGFG jaHa+xzcxPqiCG3Ko9WxWRgaJbq3uS/ARjqBPK0gE/hViejJDbPD5K8zu2HHee0= X-Google-Smtp-Source: AGHT+IG5+tdMrZ2ON9H8ZpGLg3GIka4FUXbeapzA9mauWtoPzhwuW9kisXtyN8OVl6ignL92UATEaA== X-Received: by 2002:a6b:3f8a:0:b0:7c7:97a0:d2f4 with SMTP id m132-20020a6b3f8a000000b007c797a0d2f4mr11694640ioa.9.1709064095809; Tue, 27 Feb 2024 12:01:35 -0800 (PST) Received: from [100.64.0.1] ([170.85.6.200]) by smtp.gmail.com with ESMTPSA id y90-20020a029563000000b004740d29b120sm1936267jah.111.2024.02.27.12.01.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Feb 2024 12:01:35 -0800 (PST) Message-ID: <33f16905-baab-47e8-a92f-d2543b69d704@sifive.com> Date: Tue, 27 Feb 2024 14:01:34 -0600 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH -fixes v3 1/2] riscv: Fix enabling cbo.zero when running in M-mode Content-Language: en-US To: Alexandre Ghiti Cc: Palmer Dabbelt , linux-kernel@vger.kernel.org, Conor Dooley , linux-riscv@lists.infradead.org, Stefan O'Rear , stable@vger.kernel.org, Andrew Jones References: <20240214090206.195754-1-samuel.holland@sifive.com> <20240214090206.195754-2-samuel.holland@sifive.com> <20240214-661604d82db4ef137540b762@orel> <579c9f3f-8c28-4e4e-88ce-9f266597b7bd@ghiti.fr> From: Samuel Holland In-Reply-To: <579c9f3f-8c28-4e4e-88ce-9f266597b7bd@ghiti.fr> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Alex, On 2024-02-27 1:48 PM, Alexandre Ghiti wrote: > Hi Samuel, > > On 14/02/2024 10:28, Andrew Jones wrote: >> On Wed, Feb 14, 2024 at 01:01:56AM -0800, Samuel Holland wrote: >>> When the kernel is running in M-mode, the CBZE bit must be set in the >>> menvcfg CSR, not in senvcfg. >>> >>> Cc: >>> Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") >>> Reviewed-by: Andrew Jones >>> Signed-off-by: Samuel Holland >>> --- >>> >>> (no changes since v1) >>> >>>   arch/riscv/include/asm/csr.h   | 2 ++ >>>   arch/riscv/kernel/cpufeature.c | 2 +- >>>   2 files changed, 3 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h >>> index 510014051f5d..2468c55933cd 100644 >>> --- a/arch/riscv/include/asm/csr.h >>> +++ b/arch/riscv/include/asm/csr.h >>> @@ -424,6 +424,7 @@ >>>   # define CSR_STATUS    CSR_MSTATUS >>>   # define CSR_IE        CSR_MIE >>>   # define CSR_TVEC    CSR_MTVEC >>> +# define CSR_ENVCFG    CSR_MENVCFG >>>   # define CSR_SCRATCH    CSR_MSCRATCH >>>   # define CSR_EPC    CSR_MEPC >>>   # define CSR_CAUSE    CSR_MCAUSE >>> @@ -448,6 +449,7 @@ >>>   # define CSR_STATUS    CSR_SSTATUS >>>   # define CSR_IE        CSR_SIE >>>   # define CSR_TVEC    CSR_STVEC >>> +# define CSR_ENVCFG    CSR_SENVCFG >>>   # define CSR_SCRATCH    CSR_SSCRATCH >>>   # define CSR_EPC    CSR_SEPC >>>   # define CSR_CAUSE    CSR_SCAUSE >>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >>> index 89920f84d0a3..c5b13f7dd482 100644 >>> --- a/arch/riscv/kernel/cpufeature.c >>> +++ b/arch/riscv/kernel/cpufeature.c >>> @@ -950,7 +950,7 @@ arch_initcall(check_unaligned_access_all_cpus); >>>   void riscv_user_isa_enable(void) >>>   { >>>       if (riscv_cpu_has_extension_unlikely(smp_processor_id(), >>> RISCV_ISA_EXT_ZICBOZ)) >>> -        csr_set(CSR_SENVCFG, ENVCFG_CBZE); >>> +        csr_set(CSR_ENVCFG, ENVCFG_CBZE); >>>   } >>>     #ifdef CONFIG_RISCV_ALTERNATIVE >>> --  >>> 2.43.0 >>> >> After our back and forth on how we determine the existence of the *envcfg >> CSRs, I wonder if we shouldn't put a comment above this >> riscv_user_isa_enable() function capturing the [current] decision. >> >> Something like >> >>   /* >>    * While the [ms]envcfg CSRs weren't defined until priv spec 1.12, >>    * they're assumed to be present when an extension is present which >>    * specifies [ms]envcfg bit(s). Hence, we don't do any additional >>    * priv spec version checks or CSR probes here. >>    */ > > > I was about to read the whole discussion in v2 to understand the v3...thank you > Drew :) I think it really makes sense to add this comment, do you intend to do > so Samuel? Yes, I am about to send a v4 with the changes from the previous discussion, including a RISCV_ISA_EXT_XLINUXENVCFG bit specifically for the presence of the [ms]envcfg CSR and a comment like the above. Regards, Samuel