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Tue, 04 Aug 2026 07:11:51 -0700 (PDT) Received: from pve-server ([49.205.216.49]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3158673a9e4sm6178315eec.18.2026.08.04.07.11.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Aug 2026 07:11:50 -0700 (PDT) From: Ritesh Harjani (IBM) To: Gaurav Batra , maddy@linux.ibm.com Cc: linuxppc-dev@lists.ozlabs.org, sbhat@linux.ibm.com, vaibhav@linux.ibm.com, donettom@linux.ibm.com, harshpb@linux.ibm.com, stable@vger.kernel.org Subject: Re: [PATCH v4] powerpc/pseries/iommu: Add TCEs for 16GB pages when RAM is pre-mapped In-Reply-To: Date: Tue, 04 Aug 2026 19:36:47 +0530 Message-ID: <33wum13c.ritesh.list@gmail.com> References: <20260727221437.89644-1-gbatra@linux.ibm.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Gaurav Batra writes: > Hello Ritesh, > <...> > As you correctly pointed out in the enable_ddw() code, this could lead > to EEH if > pmemory is assigned to the same power-of-2 chunk as (RAM + 16GB pages). > > It would be better to set device bus_dma_limit to pseries_ddw_max_ram > and *not* > > max_ram_pages, which in this case is the size of the DDW. > > I will fix this in my next version of the patch. Sure, thanks for veryfing that claim. > Please let me know if you have any other concerns. I will incorporate all those changes in the next version of the patch. > Nothing else. Otherwise, it looks good. > Thanks a lot for spending time and checking this code in deep. No issues. Thanks for fixing it! -ritesh