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X-CSE-ConnectionGUID: uqqIX571QXmFvl3N4fO7AA== X-CSE-MsgGUID: 1AkYx1VKTGGCDDPUc2OGgg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="29677780" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="29677780" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:03:36 -0700 X-CSE-ConnectionGUID: vJWqYolwRAW+N4d8vgbNhw== X-CSE-MsgGUID: LOvuvOzeQ2qva/5i3GfskA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="118403184" Received: from nirmoyda-mobl.ger.corp.intel.com (HELO [10.245.197.87]) ([10.245.197.87]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:03:32 -0700 Message-ID: <3865ed60-94aa-4bfc-b263-90283aef274f@linux.intel.com> Date: Fri, 25 Oct 2024 18:03:29 +0200 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] drm/xe/ufence: Flush xe ordered_wq in case of ufence timeout To: Jani Nikula , Nirmoy Das , intel-xe@lists.freedesktop.org Cc: Badal Nilawar , Matthew Auld , John Harrison , Himal Prasad Ghimiray , Lucas De Marchi , stable@vger.kernel.org, Matthew Brost References: <20241024151815.929142-1-nirmoy.das@intel.com> <87bjz9sbqs.fsf@intel.com> Content-Language: en-US From: Nirmoy Das In-Reply-To: <87bjz9sbqs.fsf@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/24/2024 6:32 PM, Jani Nikula wrote: > On Thu, 24 Oct 2024, Nirmoy Das wrote: >> Flush xe ordered_wq in case of ufence timeout which is observed >> on LNL and that points to the recent scheduling issue with E-cores. >> >> This is similar to the recent fix: >> commit e51527233804 ("drm/xe/guc/ct: Flush g2h worker in case of g2h >> response timeout") and should be removed once there is E core >> scheduling fix. >> >> v2: Add platform check(Himal) >> s/__flush_workqueue/flush_workqueue(Jani) >> >> Cc: Badal Nilawar >> Cc: Jani Nikula >> Cc: Matthew Auld >> Cc: John Harrison >> Cc: Himal Prasad Ghimiray >> Cc: Lucas De Marchi >> Cc: # v6.11+ >> Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2754 >> Suggested-by: Matthew Brost >> Signed-off-by: Nirmoy Das >> Reviewed-by: Matthew Brost >> --- >> drivers/gpu/drm/xe/xe_wait_user_fence.c | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.c b/drivers/gpu/drm/xe/xe_wait_user_fence.c >> index f5deb81eba01..78a0ad3c78fe 100644 >> --- a/drivers/gpu/drm/xe/xe_wait_user_fence.c >> +++ b/drivers/gpu/drm/xe/xe_wait_user_fence.c >> @@ -13,6 +13,7 @@ >> #include "xe_device.h" >> #include "xe_gt.h" >> #include "xe_macros.h" >> +#include "compat-i915-headers/i915_drv.h" > Sorry, you just can't use this in xe core. At all. Not even a little > bit. It's purely for i915 display compat code. > > If you need it for the LNL platform check, you need to use: > > xe->info.platform == XE_LUNARLAKE Will do that. That macro looked odd but I didn't know a better way. > > Although platform checks in xe code are generally discouraged. This issue unfortunately depending on platform instead of graphics IP. Thanks, Nirmoy > > BR, > Jani. > > > >> #include "xe_exec_queue.h" >> >> static int do_compare(u64 addr, u64 value, u64 mask, u16 op) >> @@ -155,6 +156,19 @@ int xe_wait_user_fence_ioctl(struct drm_device *dev, void *data, >> } >> >> if (!timeout) { >> + if (IS_LUNARLAKE(xe)) { >> + /* >> + * This is analogous to e51527233804 ("drm/xe/guc/ct: Flush g2h >> + * worker in case of g2h response timeout") >> + * >> + * TODO: Drop this change once workqueue scheduling delay issue is >> + * fixed on LNL Hybrid CPU. >> + */ >> + flush_workqueue(xe->ordered_wq); >> + err = do_compare(addr, args->value, args->mask, args->op); >> + if (err <= 0) >> + break; >> + } >> err = -ETIME; >> break; >> }