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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: EzPOtBU/WrcoFz2JMqKCmBzrz11Xs6TBnob5Z+2/ccdnhd1uaQ91RuUi2eJBNSMYrl41bsdvhHxKbjhdeulQHSTjwviWIeLZfPGYUCAKj0GMYUZ3xOhR7R+4UfniLE/Ts4DUioP1U9VzkVQWSouycoZBOr5zbxXSiJE5xVC1N/7iiB4mGovtsmQKJZyYDOK+ziHakiEAXaElIYvm8tsJszt+J8WzaSY5uKRFajkcKNg0w8eCp+MB9hErGEjJj/+0tBlRuYEMKzcRUNFwnSBE9xE6lID6HSKGvl3wfIU9jdzigso5K1q0Ili6HCtpl9D5yP1m6ELlOVmpv2RsNz3X2OWo0Cfx4/yE+9ns3bKlJoHCVNxSeKJDQ0YJeWfhgmhzskOEJ+tRkL3lAzbSsF4kFz05Jq/OD2IEMZ7foCKfjPpv98dy1aeINk14pc6HOkeu X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2026 19:47:51.8136 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a53f07ef-4003-4a22-5f16-08dee8f3482b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD81.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5754 On 2026-07-23 15:18, Mario Limonciello wrote: >> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c >> index 05d6915f9a6b0..079d4ccc88da6 100644 >> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c >> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c >> @@ -287,10 +287,19 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) >>        * is enabled. On DCE, vupdate is only needed in VRR mode. >>        */ >>       if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) { >> -        rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, enable); >> +        if (enable) { >> +            rc = amdgpu_irq_get(adev, &adev->vupdate_irq, irq_type); >> +            drm_dbg_vbl(crtc->dev, "Get vupdate_irq ret=%d\n", rc); >> +        } else { >> +            rc = amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type); >> +            drm_dbg_vbl(crtc->dev, "Put vupdate_irq ret=%d\n", rc); >> +        } > > For completeness in error handling, shouldn't you pass up the return code on non-zero?  It looks like it could pass up to DRM core then. It's not shown in the context here, but the rc is passed up later: https://elixir.bootlin.com/linux/v7.2-rc4/source/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c#L295 - Leo > >>       } else if (dc_supports_vrr(dm->dc->ctx->dce_version)) { >>           if (enable) { >> -            /* vblank irq on -> Only need vupdate irq in vrr mode */ >> +            /* vblank irq on -> Only need vupdate irq in vrr mode >> +             * Not ref-counted since we need explicit enable/disable >> +             * for DCE VRR handling >> +             */ >>               if (amdgpu_dm_crtc_vrr_active(acrtc_state)) >>                   rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); >>           } else {