On Wed, 25 Mar 2026, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apparently I forgot about the pipe min_voltage_level when I
> decoupled the CDCLK calculations from modesets. Even if the
> CDCLK frequency doesn't need changing we may still need to
> bump the voltage level to accommodate an increase in the
> port clock frequency.
>
> Currently, even if there is a full modeset, we won't notice the
> need to go through the full CDCLK calculations/programming,
> unless the set of enabled/active pipes changes, or the
> pipe/dbuf min CDCLK changes.
>
> Duplicate the same logic we use the pipe's min CDCLK frequency
> to also deal with its min voltage level.
>
> Note that the 'allow_voltage_level_decrease' stuff isn't
> really useful here since the min voltage level can only
> change during a full modeset. But I think sticking to the
> same approach in the three similar parts (pipe min cdclk,
> pipe min voltage level, dbuf min cdclk) is a good idea.
>
> Cc: stable@vger.kernel.org
> Tested-by: Mikhail Rudenko <mike.rudenko@gmail.com>
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15826
> Fixes: ba91b9eecb47 ("drm/i915/cdclk: Decouple cdclk from state->modeset")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Micha³ Grzelak <michal.grzelak@intel.com>

BR,
Micha³