From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Message-ID: <54BD4626.70902@gmail.com> Date: Mon, 19 Jan 2015 21:00:06 +0300 From: Dmitry Osipenko MIME-Version: 1.0 To: Stephen Warren , Thierry Reding CC: Alexandre Courbot , Peter De Schrijver , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH] ARM: tegra20: Store CPU "resettable" status in IRAM References: <1421319545-23920-1-git-send-email-digetx@gmail.com> <1421319545-23920-2-git-send-email-digetx@gmail.com> <20150119141224.GF23778@ulmo.nvidia.com> <54BD3E3E.2040801@wwwdotorg.org> <54BD41D3.7030703@gmail.com> <54BD42D0.3020107@wwwdotorg.org> In-Reply-To: <54BD42D0.3020107@wwwdotorg.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: 19.01.2015 20:45, Stephen Warren пишет: > On 01/19/2015 10:41 AM, Dmitry Osipenko wrote: >> 19.01.2015 20:26, Stephen Warren пишет: >>> Hopefully this works out. I suppose it's unlikely anyone will be >>> running code on >>> the AVP upstrem, so any potential conflict with AVP's usage of IRAM >>> isn't likely >>> to occur. >>> >> I don't see how it can conflict with AVP code. First KB of IRAM is >> reserved for reset handler. Am I missing something? >> >> From reset.h: >> >> /* The first 1K of IRAM is permanently reserved for the CPU reset >> handler */ > > I believe "CPU" in that context means AVP CPU. Still, I may not be correct, and > to be honest it's likely not too well defined even if that comment seems clear-cut. > Hmm... Suddenly I recalled that LP2 was always disabled in downstream kernel. I remember that I tried it once (couple years ago) and it didn't work, however I presume it was just broken. Now I don't feel good with it. -- Dmitry