From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f68.google.com ([74.125.82.68]:36468 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752021AbcFQRgs (ORCPT ); Fri, 17 Jun 2016 13:36:48 -0400 Received: by mail-wm0-f68.google.com with SMTP id m124so1265765wme.3 for ; Fri, 17 Jun 2016 10:36:47 -0700 (PDT) Subject: Re: [amd-gfx] [PATCH] drm/amdgpu: fix num_rbs exposed to userspace To: Alex Deucher References: <1466173225-14886-1-git-send-email-alexander.deucher@amd.com> <576417EC.7010300@gmail.com> Cc: amd-gfx@lists.freedesktop.org, Alex Deucher , "for 3.8" From: =?UTF-8?Q?Nicolai_H=c3=a4hnle?= Message-ID: <5764352D.2070206@gmail.com> Date: Fri, 17 Jun 2016 19:36:45 +0200 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: On 17.06.2016 17:37, Alex Deucher wrote: > On Fri, Jun 17, 2016 at 11:31 AM, Nicolai Hähnle wrote: >> On 17.06.2016 16:20, Alex Deucher wrote: >>> >>> This was accidently broken for harvest cards when the >>> code was refactored for Polaris support. >>> >>> Signed-off-by: Alex Deucher >>> Cc: stable@vger.kernel.org >>> --- >>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>> index 9ab28ca..e5c22cd 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>> @@ -459,7 +459,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, >>> void *data, struct drm_file >>> dev_info.max_memory_clock = adev->pm.default_mclk >>> * 10; >>> } >>> dev_info.enabled_rb_pipes_mask = >>> adev->gfx.config.backend_enable_mask; >>> - dev_info.num_rb_pipes = adev->gfx.config.num_rbs; >>> + dev_info.num_rb_pipes = >>> adev->gfx.config.max_backends_per_se; >> >> >> At a glance, that looks suspicious to me. num_rb_pipes becomes rb_pipes in >> libdrmm and then num_render_backends. We divide num_render_backends by the >> number of SEs * SHs in radeonsi. >> >> In a nutshell, radeonsi expects this to be the total number of RBs >> (including disabled/harvested ones). > > Right. that's what this patch does. > adev->gfx.config.max_backends_per_se is the total number of RBs per SE > available on the asic. adev->gfx.config.num_rbs is the total number of > enabled RBs (max - disabled). For non-harvest cards, they are the > same. But the total number of RBs is different from the total number of RBs per SE... Nicolai > > Alex > >> >> Nicolai >> >> >>> dev_info.num_hw_gfx_contexts = >>> adev->gfx.config.max_hw_contexts; >>> dev_info._pad = 0; >>> dev_info.ids_flags = 0; >>> >>