From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailout4.samsung.com ([203.254.224.34]:59846 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751025AbcL3Ghp (ORCPT ); Fri, 30 Dec 2016 01:37:45 -0500 MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: 8BIT Message-id: <586600B5.1000903@samsung.com> Date: Fri, 30 Dec 2016 15:37:41 +0900 From: Chanwoo Choi To: Andi Shyti , Tomasz Figa , Krzysztof Kozlowski , Sylwester Nawrocki , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Kukjin Kim , Javier Martinez Canillas , Linus Walleij Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Andi Shyti Subject: Re: [PATCH v2 2/4] pinctrl: dt-bindings: samsung: add drive strength macros for Exynos5433 In-reply-to: <20161230041421.24448-3-andi.shyti@samsung.com> References: <20161230041421.24448-1-andi.shyti@samsung.com> <20161230041421.24448-3-andi.shyti@samsung.com> Sender: stable-owner@vger.kernel.org List-ID: Hi Andi, On 2016년 12월 30일 13:14, Andi Shyti wrote: > Commit 5db7e3bb87df ("pinctrl: dt-bindings: samsung: Add header with > values used for configuration") has added a header file for defining the > pinctrl values in order to avoid hardcoded settings in the Exynos > DTS related files. > > Extend samsung.h to the Exynos5433 for drive strength values > which are strictly related to the particular SoC and may defer > from others. > > Signed-off-by: Andi Shyti > --- > include/dt-bindings/pinctrl/samsung.h | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h > index 6276eb785e2b..e0ebb20ffdd3 100644 > --- a/include/dt-bindings/pinctrl/samsung.h > +++ b/include/dt-bindings/pinctrl/samsung.h > @@ -45,6 +45,20 @@ > #define EXYNOS5420_PIN_DRV_LV3 2 > #define EXYNOS5420_PIN_DRV_LV4 3 > > +/* Drive strengths for Exynos5433 */ > +#define EXYNOS5433_PIN_DRV_FAST_SR1 0 > +#define EXYNOS5433_PIN_DRV_FAST_SR2 1 > +#define EXYNOS5433_PIN_DRV_FAST_SR3 2 > +#define EXYNOS5433_PIN_DRV_FAST_SR4 3 > +#define EXYNOS5433_PIN_DRV_FAST_SR5 4 > +#define EXYNOS5433_PIN_DRV_FAST_SR6 5 > +#define EXYNOS5433_PIN_DRV_SLOW_SR1 8 > +#define EXYNOS5433_PIN_DRV_SLOW_SR2 9 > +#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa > +#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb > +#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc > +#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf > + > #define EXYNOS_PIN_FUNC_INPUT 0 > #define EXYNOS_PIN_FUNC_OUTPUT 1 > #define EXYNOS_PIN_FUNC_2 2 > Looks good to me. ('SR' means "Slew Rate".) Reviewed-by: Chanwoo Choi -- Regards, Chanwoo Choi