* [PATCH] PCI: Fix MSI disabled for HiSilicon Hip06/Hip07 EP mode
@ 2017-12-28 9:53 Dongdong Liu
2018-01-03 6:56 ` Zhou Wang
2018-01-13 0:04 ` Bjorn Helgaas
0 siblings, 2 replies; 3+ messages in thread
From: Dongdong Liu @ 2017-12-28 9:53 UTC (permalink / raw)
To: helgaas
Cc: linux-pci, linuxarm, zhouyupeng1, tangyongqian, bruce.feng,
Dongdong Liu, stable
HiSilicon Hip06/Hip07 can work as RC mode and EP mode. The PCIe Root Port
in Hip06/Hip07 SoCs advertises an MSI capability, but it can not generate
MSIs. It can generate MSIs When it works as EP mode, but the vendor id and
device id of RP and EP are the same. Current code also disable MSI for EP
mode, we only need to disable MSI for Root Port.
Cc: <stable@vger.kernel.org>
Fixes: 72f2ff0deb87 ("PCI: Disable MSI for HiSilicon Hip06/Hip07 Root Ports")
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
---
drivers/pci/quirks.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 10684b1..d22750e 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1636,8 +1636,8 @@ static void quirk_pcie_mch(struct pci_dev *pdev)
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch);
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
/*
* It's possible for the MSI to get corrupted if shpc and acpi
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] PCI: Fix MSI disabled for HiSilicon Hip06/Hip07 EP mode
2017-12-28 9:53 [PATCH] PCI: Fix MSI disabled for HiSilicon Hip06/Hip07 EP mode Dongdong Liu
@ 2018-01-03 6:56 ` Zhou Wang
2018-01-13 0:04 ` Bjorn Helgaas
1 sibling, 0 replies; 3+ messages in thread
From: Zhou Wang @ 2018-01-03 6:56 UTC (permalink / raw)
To: Dongdong Liu, helgaas
Cc: linux-pci, linuxarm, stable, tangyongqian, bruce.feng
On 2017/12/28 17:53, Dongdong Liu wrote:
> HiSilicon Hip06/Hip07 can work as RC mode and EP mode. The PCIe Root Port
> in Hip06/Hip07 SoCs advertises an MSI capability, but it can not generate
> MSIs. It can generate MSIs When it works as EP mode, but the vendor id and
> device id of RP and EP are the same. Current code also disable MSI for EP
> mode, we only need to disable MSI for Root Port.
>
> Cc: <stable@vger.kernel.org>
> Fixes: 72f2ff0deb87 ("PCI: Disable MSI for HiSilicon Hip06/Hip07 Root Ports")
> Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
It looks good to me, so:
Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com>
Thanks,
Zhou
> ---
> drivers/pci/quirks.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 10684b1..d22750e 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -1636,8 +1636,8 @@ static void quirk_pcie_mch(struct pci_dev *pdev)
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
> -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch);
>
> +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
>
> /*
> * It's possible for the MSI to get corrupted if shpc and acpi
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] PCI: Fix MSI disabled for HiSilicon Hip06/Hip07 EP mode
2017-12-28 9:53 [PATCH] PCI: Fix MSI disabled for HiSilicon Hip06/Hip07 EP mode Dongdong Liu
2018-01-03 6:56 ` Zhou Wang
@ 2018-01-13 0:04 ` Bjorn Helgaas
1 sibling, 0 replies; 3+ messages in thread
From: Bjorn Helgaas @ 2018-01-13 0:04 UTC (permalink / raw)
To: Dongdong Liu
Cc: linux-pci, linuxarm, zhouyupeng1, tangyongqian, bruce.feng,
stable
On Thu, Dec 28, 2017 at 05:53:32PM +0800, Dongdong Liu wrote:
> HiSilicon Hip06/Hip07 can work as RC mode and EP mode. The PCIe Root Port
> in Hip06/Hip07 SoCs advertises an MSI capability, but it can not generate
> MSIs. It can generate MSIs When it works as EP mode, but the vendor id and
> device id of RP and EP are the same. Current code also disable MSI for EP
> mode, we only need to disable MSI for Root Port.
>
> Cc: <stable@vger.kernel.org>
> Fixes: 72f2ff0deb87 ("PCI: Disable MSI for HiSilicon Hip06/Hip07 Root Ports")
> Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Applied with Zhou's reviewed-by to pci/msi for v4.16, thanks!
> ---
> drivers/pci/quirks.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 10684b1..d22750e 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -1636,8 +1636,8 @@ static void quirk_pcie_mch(struct pci_dev *pdev)
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
> -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch);
>
> +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
>
> /*
> * It's possible for the MSI to get corrupted if shpc and acpi
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2018-01-13 0:04 UTC | newest]
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2017-12-28 9:53 [PATCH] PCI: Fix MSI disabled for HiSilicon Hip06/Hip07 EP mode Dongdong Liu
2018-01-03 6:56 ` Zhou Wang
2018-01-13 0:04 ` Bjorn Helgaas
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