From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-f65.google.com ([209.85.221.65]:39946 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730677AbeKNCkF (ORCPT ); Tue, 13 Nov 2018 21:40:05 -0500 Received: by mail-wr1-f65.google.com with SMTP id p4so4892608wrt.7 for ; Tue, 13 Nov 2018 08:41:12 -0800 (PST) Message-ID: <5BEAFEA5.6060902@baylibre.com> Date: Tue, 13 Nov 2018 17:41:09 +0100 From: Neil Armstrong MIME-Version: 1.0 To: stable@vger.kernel.org CC: Jerome Brunet , Carlo Caione , Kevin Hilman , Christian Hewitt , Michael Turquette , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL References: <20181105230820.3562-1-jbrunet@baylibre.com> <5BEAFE05.9070905@baylibre.com> In-Reply-To: <5BEAFE05.9070905@baylibre.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: Le 13/11/2018 17:38, Neil Armstrong a �crit : > Hi Stable team, > > Le 06/11/2018 00:08, Jerome Brunet a �crit : >> From: Christian Hewitt >> >> On the Khadas VIM2 (GXM) and LePotato (GXL) board there are problems >> with reboot; e.g. a ~60 second delay between issuing reboot and the >> board power cycling (and in some OS configurations reboot will fail >> and require manual power cycling). >> >> Similar to 'commit c987ac6f1f088663b6dad39281071aeb31d450a8 ("clk: >> meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL")' the SCPI Cortex-M4 >> Co-Processor seems to depend on FCLK_DIV3 being operational. >> >> Until commit 05f814402d6174369b3b29832cbb5eb5ed287059 ("clk: >> meson: add fdiv clock gates"), this clock was modeled and left on by >> the bootloader. >> >> We don't have precise documentation about the SCPI Co-Processor and >> its clock requirement so we are learning things the hard way. >> >> Marking this clock as critical solves the problem but it should not >> be viewed as final solution. Ideally, the SCPI driver should claim >> these clocks. We also depends on some clock hand-off mechanism >> making its way to CCF, to make sure the clock stays on between its >> registration and the SCPI driver probe. >> >> Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates") >> Signed-off-by: Christian Hewitt >> Signed-off-by: Jerome Brunet > > > Could this patch go into the next 4.18 stable release since it hit linus master with commit id e2576c8bdfd462c34b8a46c0084e7c30b0851bf4 ? I forgot, but it should also go into the next 4.19 stable release aswell. Neil > Thanks, > Neil > >> --- >> drivers/clk/meson/gxbb.c | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> >> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c >> index 9309cfaaa464..4ada9668fd49 100644 >> --- a/drivers/clk/meson/gxbb.c >> +++ b/drivers/clk/meson/gxbb.c >> @@ -506,6 +506,18 @@ static struct clk_regmap gxbb_fclk_div3 = { >> .ops = &clk_regmap_gate_ops, >> .parent_names = (const char *[]){ "fclk_div3_div" }, >> .num_parents = 1, >> + /* >> + * FIXME: >> + * This clock, as fdiv2, is used by the SCPI FW and is required >> + * by the platform to operate correctly. >> + * Until the following condition are met, we need this clock to >> + * be marked as critical: >> + * a) The SCPI generic driver claims and enable all the clocks >> + * it needs >> + * b) CCF has a clock hand-off mechanism to make the sure the >> + * clock stays on until the proper driver comes along >> + */ >> + .flags = CLK_IS_CRITICAL, >> }, >> }; >> >>