public inbox for stable@vger.kernel.org
 help / color / mirror / Atom feed
From: Leo Li <sunpeng.li@amd.com>
To: Alex Deucher <alexdeucher@gmail.com>
Cc: <amd-gfx@lists.freedesktop.org>, <Harry.Wentland@amd.com>,
	<Aurabindo.Pillai@amd.com>, <mario.limonciello@amd.com>,
	<wiagn233@outlook.com>, <sysdadmin@m1k.cloud>,
	<stable@vger.kernel.org>
Subject: Re: [PATCH] drm/amd/display: Restore 5s vbl offdelay for NV3x+ DGPUs
Date: Wed, 22 Apr 2026 13:19:02 -0400	[thread overview]
Message-ID: <5b0ea1b1-40be-4941-b4cc-521a9fca8c09@amd.com> (raw)
In-Reply-To: <CADnq5_OYNSoWteuXDJrCOtj4qYn2q+vyXUKZaHvgNN+5xFFg2Q@mail.gmail.com>



On 2026-04-22 12:56, Alex Deucher wrote:
> On Wed, Apr 22, 2026 at 12:49 PM <sunpeng.li@amd.com> wrote:
>>
>> From: Leo Li <sunpeng.li@amd.com>
>>
>> [Why]
>>
>> Rapid vblank off is causing flip-done timeouts for NV3x and newer
>> family of GPUs that support more idle optimization features.
>>
>> A proper fix requires further investigation. In lieu of it, let's
>> workaround it for now.
>>
>> [How]
>>
>> For NV3x and newer family of DGPUs, restore the old 5s vblank off timer.
>>
>> Fixes: 9b47278cec98 ("drm/amd/display: temp w/a for dGPU to enter idle optimizations")
>> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3787
>> Link: https://lore.kernel.org/amd-gfx/20260217191632.1243826-1-sysdadmin@m1k.cloud/
>> Signed-off-by: Leo Li <sunpeng.li@amd.com>
>> Tested-by: Michele Palazzi <sysdadmin@m1k.cloud>
>> ---
>>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 18 +++++++++++++++---
>>  1 file changed, 15 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 3fa4dbda4517c..ce5063928413c 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -9511,9 +9511,21 @@ static void manage_dm_interrupts(struct amdgpu_device *adev,
>>         if (acrtc_state) {
>>                 timing = &acrtc_state->stream->timing;
>>
>> -               if (amdgpu_ip_version(adev, DCE_HWIP, 0) <
>> -                          IP_VERSION(3, 5, 0) ||
>> -                          !(adev->flags & AMD_IS_APU)) {
>> +               if (amdgpu_ip_version(adev, DCE_HWIP, 0) >=
>> +                     IP_VERSION(3, 2, 0) &&
>> +                     !(adev->flags & AMD_IS_APU)) {
> 
> Why only dGPUs?  Seems like this is reported as least as often on APUs
> if not more.
> 
> Alex

Hi Alex, Mario,

At least in the case of the few reporters I was working with, this specific
flip-done timeout was reproduced on NV3x and 4x systems running multi-display.
The reporter for the linked gitlab issue was also running a nv3.

The cause of these flip timeouts can be varied. The signature for this
particular issue was OTG failing to fire an interrupt that is expected to
deliver the flip-done event. I'm not aware of this particular signature in APUs
-- at least none on my radar. Do bring it to my attention if you're aware of
them.

Thanks,
Leo

> 
>> +                       /*
>> +                        * DGPUs NV3x and newer that support idle optimizations
>> +                        * experience intermittent flip-done timeouts on cursor
>> +                        * updates. Restore 5s offdelay behavior for now.
>> +                        *
>> +                        * Discussion on the issue:
>> +                        * https://lore.kernel.org/amd-gfx/20260217191632.1243826-1-sysdadmin@m1k.cloud/
>> +                        */
>> +                       config.offdelay_ms = 5000;
>> +                       config.disable_immediate = false;
>> +               } else if (amdgpu_ip_version(adev, DCE_HWIP, 0) <
>> +                            IP_VERSION(3, 5, 0)) {
>>                         /*
>>                          * Older HW and DGPU have issues with instant off;
>>                          * use a 2 frame offdelay.
>> --
>> 2.53.0
>>


  reply	other threads:[~2026-04-22 17:19 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-22 16:29 [PATCH] drm/amd/display: Restore 5s vbl offdelay for NV3x+ DGPUs sunpeng.li
2026-04-22 16:42 ` Mario Limonciello
2026-04-22 16:56 ` Alex Deucher
2026-04-22 17:19   ` Leo Li [this message]
2026-04-22 17:42     ` Mario Limonciello
2026-04-22 17:50       ` Michele Palazzi
2026-04-22 17:52         ` Mario Limonciello

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=5b0ea1b1-40be-4941-b4cc-521a9fca8c09@amd.com \
    --to=sunpeng.li@amd.com \
    --cc=Aurabindo.Pillai@amd.com \
    --cc=Harry.Wentland@amd.com \
    --cc=alexdeucher@gmail.com \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=mario.limonciello@amd.com \
    --cc=stable@vger.kernel.org \
    --cc=sysdadmin@m1k.cloud \
    --cc=wiagn233@outlook.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox