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[93.42.70.190]) by smtp.gmail.com with ESMTPSA id w20-20020a056402071400b0043a87e6196esm129683edx.6.2022.07.08.18.03.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 18:03:36 -0700 (PDT) Message-ID: <62c8d3e8.1c69fb81.26eee.0249@mx.google.com> X-Google-Original-Message-ID: Date: Sat, 9 Jul 2022 03:03:34 +0200 From: Christian Marangi To: Bjorn Helgaas Cc: Stanimir Varbanov , Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Rob Herring , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH] PCI: qcom: Enable clocks only after PARF_PHY setup for rev 2.1.0 References: <20220708222743.27019-1-ansuelsmth@gmail.com> <20220708230155.GA388993@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220708230155.GA388993@bhelgaas> Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Fri, Jul 08, 2022 at 06:01:55PM -0500, Bjorn Helgaas wrote: > On Sat, Jul 09, 2022 at 12:27:43AM +0200, Christian Marangi wrote: > > We currently enable clocks BEFORE we write to PARF_PHY_CTRL reg to > > enable clocks and resets. This case the driver to never set to a ready > > state with the error 'Phy link never came up'. > > > > This in fact is caused by the phy clock getting enabled before setting > > the required bits in the PARF regs. > > > > A workaround for this was set but with this new discovery we can drop > > the workaround and use a proper solution to the problem by just enabling > > the clock only AFTER the PARF_PHY_CTRL bit is set. > > > > This correctly setup the pcie line and makes it usable even when a > > bootloader leave the pcie line to a underfined state. > > Is "pcie" here a signal name? Maybe this refers to the "PCIe link"? > Hi, no i was referring to PCIe link. Fell free to fix it if it's not a problem (or if you want i can just resend) > > Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") > > Cc: stable@vger.kernel.org # v5.4+ > > Signed-off-by: Christian Marangi > > Thanks, I put this on > https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git, > pci/ctrl/qcom-pending branch (head 47b4ec9d2e60). > > Can you take a look and make sure I didn't mess up the conflict > resolution with the rest of the series? Think something went wrong in the rebase as the patch fixup is reverted. 11946f8b6e77a6794c111aafef7772e9967d9a54 is still wrong. clk_bulk_prepare_enable must be after writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); so in the post init. > > > --- > > drivers/pci/controller/dwc/pcie-qcom.c | 10 ++++------ > > 1 file changed, 4 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > > index 2ea13750b492..da13a66ced14 100644 > > --- a/drivers/pci/controller/dwc/pcie-qcom.c > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > > @@ -337,8 +337,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) > > reset_control_assert(res->ext_reset); > > reset_control_assert(res->phy_reset); > > > > - writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); > > - > > ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); > > if (ret < 0) { > > dev_err(dev, "cannot enable regulators\n"); > > @@ -381,15 +379,15 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) > > goto err_deassert_axi; > > } > > > > - ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); > > - if (ret) > > - goto err_clks; > > - > > /* enable PCIe clocks and resets */ > > val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); > > val &= ~BIT(0); > > writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); > > > > + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); > > + if (ret) > > + goto err_clks; > > + > > if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || > > of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { > > writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | > > -- > > 2.36.1 > > -- Ansuel