From: Ira Weiny <ira.weiny@intel.com>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Davidlohr Bueso" <dave@stgolabs.net>,
"Jonathan Cameron" <jonathan.cameron@huawei.com>,
"Dave Jiang" <dave.jiang@intel.com>,
"Alison Schofield" <alison.schofield@intel.com>,
"Vishal Verma" <vishal.l.verma@intel.com>,
"Ira Weiny" <ira.weiny@intel.com>,
"Dan Williams" <dan.j.williams@intel.com>,
"Ben Widawsky" <bwidawsk@kernel.org>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>, stable@vger.kernel.org
Subject: Re: [PATCH 1/1] cxl/pci: Convert PCIBIOS_* return codes to errnos
Date: Wed, 29 May 2024 08:30:34 -0500 [thread overview]
Message-ID: <66572dfaa49c9_86b8f294d2@iweiny-mobl.notmuch> (raw)
In-Reply-To: <20240527123403.13098-1-ilpo.jarvinen@linux.intel.com>
Ilpo Järvinen wrote:
> pci_{read,write}_config_*word() and pcie_capability_read_word() return
> PCIBIOS_* codes, not usual errnos.
>
> Fix return value checks to handle PCIBIOS_* return codes correctly by
> dropping < 0 from the check and convert the PCIBIOS_* return codes into
> errnos using pcibios_err_to_errno() before returning them.
>
> Fixes: ce17ad0d5498 ("cxl: Wait Memory_Info_Valid before access memory related info")
> Fixes: 34e37b4c432c ("cxl/port: Enable HDM Capability after validating DVSEC Ranges")
> Fixes: 14d788740774 ("cxl/mem: Consolidate CXL DVSEC Range enumeration in the core")
> Fixes: 560f78559006 ("cxl/pci: Retrieve CXL DVSEC memory info")
> Cc: stable@vger.kernel.org
> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
[snip]
prev parent reply other threads:[~2024-05-29 13:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-27 12:34 [PATCH 1/1] cxl/pci: Convert PCIBIOS_* return codes to errnos Ilpo Järvinen
2024-05-28 22:20 ` Alison Schofield
2024-05-29 12:19 ` Ilpo Järvinen
2024-05-29 16:43 ` Alison Schofield
2024-05-29 13:30 ` Ira Weiny [this message]
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